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authorTim Wawrzynczak <twawrzynczak@chromium.org>2022-08-16 14:18:35 -0600
committerFelix Held <felix-coreboot@felixheld.de>2022-08-18 18:28:04 +0000
commitbcc3059d83b7503a3247690a895a05127102d414 (patch)
treee4bc9164ab74f4946444d3d1966803fc726689ad /src/cpu/x86
parentc1de4b456b9fe9a4b79112e103ce5ee41ba837f7 (diff)
mb/google/brya/var/agah: Update NVVDD VR PGOOD GPIO
For board revs 3 and later, the PG pin for the NVVDD VR moved from GPP_E16 to GPP_E3. To accommodate this, the DSDT contains a Name that this code will write the correct GPIO # to depending on the board rev, and we'll use that instead. BUG=b:239721380 TEST=still works on board rev 2 Signed-off-by: Tim Wawrzynczak <twawrzynczak@chromium.org> Change-Id: I11aec6069da8e086789419303871c6d0f5fb29af Reviewed-on: https://review.coreboot.org/c/coreboot/+/66806 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com> Reviewed-by: Ivy Jian <ivy.jian@quanta.corp-partner.google.com>
Diffstat (limited to 'src/cpu/x86')
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