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authorKyösti Mälkki <kyosti.malkki@gmail.com>2021-06-06 16:58:19 +0300
committerKyösti Mälkki <kyosti.malkki@gmail.com>2021-06-10 17:47:59 +0000
commit242f1d962f24193499795106466923e1f78a4485 (patch)
tree1c1d7be30459dfc89523759905ae14b044c04c91 /src/cpu/x86
parent0cfa9110b6d004777cca991771d74ed8dcf5c0e4 (diff)
cpu/x86/lapic: Do not inline some utility functions
They are not __always_inline and specially enable_lapic() will become more complex to support X2APIC state changes. Change-Id: Ic180fa8b36e419aba07e1754d4bf48c9dfddb2f3 Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/55258 Reviewed-by: Angel Pons <th3fanbus@gmail.com> Reviewed-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-by: Wonkyu Kim <wonkyu.kim@intel.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Diffstat (limited to 'src/cpu/x86')
-rw-r--r--src/cpu/x86/lapic/Makefile.inc7
-rw-r--r--src/cpu/x86/lapic/lapic.c37
2 files changed, 42 insertions, 2 deletions
diff --git a/src/cpu/x86/lapic/Makefile.inc b/src/cpu/x86/lapic/Makefile.inc
index ea160148cf..8e89d29f68 100644
--- a/src/cpu/x86/lapic/Makefile.inc
+++ b/src/cpu/x86/lapic/Makefile.inc
@@ -1,4 +1,3 @@
-ramstage-y += lapic.c
ramstage-y += lapic_cpu_init.c
ramstage-$(CONFIG_SMP) += secondary.S
bootblock-$(CONFIG_UDELAY_LAPIC) += apic_timer.c
@@ -10,3 +9,9 @@ verstage_x86-y += boot_cpu.c
romstage-y += boot_cpu.c
ramstage-y += boot_cpu.c
postcar-y += boot_cpu.c
+
+bootblock-y += lapic.c
+verstage_x86-y += lapic.c
+romstage-y += lapic.c
+ramstage-y += lapic.c
+postcar-y += lapic.c
diff --git a/src/cpu/x86/lapic/lapic.c b/src/cpu/x86/lapic/lapic.c
index 468a5dc256..9f3cff5834 100644
--- a/src/cpu/x86/lapic/lapic.c
+++ b/src/cpu/x86/lapic/lapic.c
@@ -1,10 +1,37 @@
/* SPDX-License-Identifier: GPL-2.0-only */
#include <cpu/x86/lapic.h>
+#include <cpu/x86/lapic_def.h>
+#include <cpu/x86/msr.h>
#include <console/console.h>
#include <stdint.h>
-void lapic_virtual_wire_mode_init(void)
+void enable_lapic(void)
+{
+ msr_t msr;
+ msr = rdmsr(LAPIC_BASE_MSR);
+ msr.hi &= 0xffffff00;
+ msr.lo &= ~LAPIC_BASE_MSR_ADDR_MASK;
+ msr.lo |= LAPIC_DEFAULT_BASE;
+ msr.lo |= LAPIC_BASE_MSR_ENABLE;
+ wrmsr(LAPIC_BASE_MSR, msr);
+}
+
+void disable_lapic(void)
+{
+ msr_t msr;
+ msr = rdmsr(LAPIC_BASE_MSR);
+ msr.lo &= ~LAPIC_BASE_MSR_ENABLE;
+ wrmsr(LAPIC_BASE_MSR, msr);
+}
+
+/* See if I need to initialize the local APIC */
+static int need_lapic_init(void)
+{
+ return CONFIG(SMP) || CONFIG(IOAPIC);
+}
+
+static void lapic_virtual_wire_mode_init(void)
{
/* this is so interrupts work. This is very limited scope --
* linux will do better later, we hope ...
@@ -40,3 +67,11 @@ void lapic_virtual_wire_mode_init(void)
printk(BIOS_DEBUG, " apic_id: 0x%x ", lapicid());
printk(BIOS_INFO, "done.\n");
}
+
+void setup_lapic(void)
+{
+ if (need_lapic_init())
+ lapic_virtual_wire_mode_init();
+ else
+ disable_lapic();
+}