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| author | Jason Schildt <jschildt@gmail.com> | 2005-10-25 21:07:34 +0000 |
|---|---|---|
| committer | Jason Schildt <jschildt@gmail.com> | 2005-10-25 21:07:34 +0000 |
| commit | 6a2c09a386970257188824f8901706c5579d5b50 (patch) | |
| tree | ef088374ccd411c4eebefb788f9efec686dbbd4b /src/cpu/x86 | |
| parent | c9c4dd65ac5892530b70d93f586fe1de9f0bc1f7 (diff) | |
- See Issue Tracker ID-3 "lnxi-patch3"
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@2067 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
Diffstat (limited to 'src/cpu/x86')
| -rw-r--r-- | src/cpu/x86/mtrr/earlymtrr.c | 13 |
1 files changed, 13 insertions, 0 deletions
diff --git a/src/cpu/x86/mtrr/earlymtrr.c b/src/cpu/x86/mtrr/earlymtrr.c index 105f7c49df..aea8e258d4 100644 --- a/src/cpu/x86/mtrr/earlymtrr.c +++ b/src/cpu/x86/mtrr/earlymtrr.c @@ -117,4 +117,17 @@ static void early_mtrr_init(void) enable_cache(); } +static int early_mtrr_init_detected(void) +{ + msr_t msr; + /* See if MTRR's are enabled. + * a #RESET disables them while an #INIT + * preserves their state. This works + * on both Intel and AMD cpus, at least + * according to the documentation. + */ + msr = rdmsr(MTRRdefType_MSR); + return msr.lo & 0x00000800; +} + #endif /* EARLYMTRR_C */ |