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| author | Angel Pons <th3fanbus@gmail.com> | 2022-02-14 13:04:34 +0100 |
|---|---|---|
| committer | Felix Held <felix-coreboot@felixheld.de> | 2022-02-24 01:18:03 +0000 |
| commit | e2531ffaa87be5c26005ff986db8492a03f809e3 (patch) | |
| tree | 843fb04a1551f4b5173aefbd9ad31e93eeead96c /src/cpu/x86/tsc | |
| parent | fdb0294846cf18b1077e8b0a4b2fe29d6b5a0bb4 (diff) | |
nb/intel/ironlake: Move out HECI remainders into southbridge
Move the remaining HECI-related stuff to southbridge scope, as the HECI
hardware is in the southbridge. Note that HECI BAR is now enabled a bit
earlier than before, but this shouldn't matter.
Change-Id: I4a29d0b5d5c5e22508bcdfe34a1c5459ae967c75
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/61932
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
Diffstat (limited to 'src/cpu/x86/tsc')
0 files changed, 0 insertions, 0 deletions