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authorXavi Drudis Ferran <xdrudis@tinet.cat>2011-02-28 03:49:28 +0000
committerMarc Jones <marc.jones@amd.com>2011-02-28 03:49:28 +0000
commitc3132105bdd35ba174cd0938847ebf292e2eda26 (patch)
tree93ba80ba0453fd5c5b4699dc386607fd9b9736ca /src/cpu/x86/tsc
parent6276b6f151e050f0470fa7f1c5a2d73ff3f65282 (diff)
Improving BKDG implementation of P-states,
CPU and northbridge frequency and voltage handling for Fam 10 in SVI mode. In fact I changed coreDelay before deleting the code in fidvid that called it. But there're still a couple of calls from src/northbridge/amd/amdmct/wrappers/mcti_d.c Since the comment encouraged fixing something, I parametrized it with the delay time in microseconds and paranoically tried to avoid an overflow at pathological moments. Signed-off-by: Xavi Drudis Ferran <xdrudis@tinet.cat> Acked-by: Marc Jones <marcj303@gmail.com> git-svn-id: svn://svn.coreboot.org/coreboot/trunk@6408 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
Diffstat (limited to 'src/cpu/x86/tsc')
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