diff options
| author | Aaron Durbin <adurbin@chromium.org> | 2015-09-29 16:31:20 -0500 |
|---|---|---|
| committer | Aaron Durbin <adurbin@chromium.org> | 2015-10-14 17:07:52 +0000 |
| commit | 75c51d9af15dfc599adaf7a8f6e892d452146f9c (patch) | |
| tree | c4232740e4f08e94947dbe821bdccb0b43909b77 /src/cpu/x86/tsc | |
| parent | e3d2d6fd70ed932c98ac19f6294cb610d27fa7bf (diff) | |
x86: add standalone verstage support
To support x86 verstage one needs a working buffer for
vboot. That buffer resides in the cache-as-ram region
which persists across verstage and romstage. The current
assumption is that verstage brings cache-as-ram up
and romstage tears cache-as-ram down. The timestamp,
cbmem console, and the vboot work buffer are persistent
through in both romstage and verstage. The vboot
work buffer as well as the cbmem console are permanently
destroyed once cache-as-ram is torn down. The timestamp
region is migrated. When verstage is enabled the assumption
is that _start is the romstage entry point. It's currently
expected that the chipset provides the entry point to
romstage when verstage is employed. Also, the car_var_*()
APIs use direct access when in verstage since its expected
verstage does not tear down cache-as-ram. Lastly, supporting
files were added to verstage-y such that an x86 verstage
will build and link.
BUG=chrome-os-partner:44827
BRANCH=None
TEST=Built and booted glados using separate verstage.
Change-Id: I097aa0b92f3bb95275205a3fd8b21362c67b97aa
Signed-off-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-on: http://review.coreboot.org/11822
Tested-by: build bot (Jenkins)
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
Diffstat (limited to 'src/cpu/x86/tsc')
| -rw-r--r-- | src/cpu/x86/tsc/Makefile.inc | 1 |
1 files changed, 1 insertions, 0 deletions
diff --git a/src/cpu/x86/tsc/Makefile.inc b/src/cpu/x86/tsc/Makefile.inc index 600f3131b7..bbebda9172 100644 --- a/src/cpu/x86/tsc/Makefile.inc +++ b/src/cpu/x86/tsc/Makefile.inc @@ -1,5 +1,6 @@ ramstage-$(CONFIG_UDELAY_TSC) += delay_tsc.c romstage-$(CONFIG_TSC_CONSTANT_RATE) += delay_tsc.c +verstage-$(CONFIG_TSC_CONSTANT_RATE) += delay_tsc.c ifeq ($(CONFIG_HAVE_SMI_HANDLER),y) smm-$(CONFIG_TSC_CONSTANT_RATE) += delay_tsc.c endif |