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| author | David Hendricks <dhendrix@chromium.org> | 2013-08-08 16:16:40 -0700 |
|---|---|---|
| committer | Patrick Georgi <patrick@georgi-clan.de> | 2013-12-21 22:46:28 +0100 |
| commit | 5f6ffbab1b67ed34aac4b85ae9e64dbd08e373f2 (patch) | |
| tree | 2d1286cdbdcdf40ec79541057b8fc668b50e0492 /src/cpu/x86/sse_enable.inc | |
| parent | bd56bf0dcff59d38066715438a9350f50136fcc3 (diff) | |
exynos5420: add CPLL and DPLL to the known list of PLLs
This patch adds CPLL and DPLL to the known list of PLLs.
This is ported from https://gerrit.chromium.org/gerrit/#/c/62617/
Signed-off-by: David Hendricks <dhendrix@chromium.org>
Change-Id: I2f2614e44cd9c98d98b8db9347f29de21703d1af
Reviewed-on: https://gerrit.chromium.org/gerrit/65282
Reviewed-by: Gabe Black <gabeblack@chromium.org>
Tested-by: David Hendricks <dhendrix@chromium.org>
Commit-Queue: David Hendricks <dhendrix@chromium.org>
Reviewed-on: http://review.coreboot.org/4461
Tested-by: build bot (Jenkins)
Reviewed-by: Patrick Georgi <patrick@georgi-clan.de>
Diffstat (limited to 'src/cpu/x86/sse_enable.inc')
0 files changed, 0 insertions, 0 deletions