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authorJulius Werner <jwerner@chromium.org>2017-09-01 14:27:46 -0700
committerJulius Werner <jwerner@chromium.org>2017-09-06 23:26:47 +0000
commit2be64048c1cc775c49d9179501e9c51dd307ba72 (patch)
tree6c90ce7cc65a2ca6e46dd0740a5a028343b117d3 /src/cpu/x86/smm
parent64df52e269d5ec2c04bd7b65381b21d6966326af (diff)
google/gru: Re-enable 3V rail GPIO on Scarlet
We've decided to move control for the 3.0V rail (technically 3.3V on Scarlet, but who cares about millivolts) back to a GPIO on the AP for Scarlet rev2. This patch adds the necessary code to enable it and make ARM TF aware of its existence. Since the pin had previously not been connected to anything, we shouldn't really need to guard this by board ID... older Scarlets will just be twiddling an empty pin. Change-Id: I6037aa486b50119f2c7b859b966cadc3686e3459 Signed-off-by: Julius Werner <jwerner@chromium.org> Reviewed-on: https://review.coreboot.org/21328 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: David Schneider <dnschneid@chromium.org>
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