diff options
| author | Aaron Durbin <adurbin@chromium.org> | 2012-10-30 09:03:43 -0500 |
|---|---|---|
| committer | Ronald G. Minnich <rminnich@gmail.com> | 2013-03-14 01:44:40 +0100 |
| commit | 76c3700f02f79b49fec30d6ef18d336f122cbf50 (patch) | |
| tree | cb1c750ef3946e2ae462e1847ec89946579274b2 /src/cpu/x86/smm/smmhandler_tseg.S | |
| parent | cc86e63e835ab0bceb62215460a13266a791cdd3 (diff) | |
haswell: Add initial support for Haswell platforms
The Haswell parts use a PCH code named Lynx Point (Series 8). Therefore,
the southbridge support is included as well. The basis for this code is
the Sandybridge code. Management Engine, IRQ routing, and ACPI still requires
more attention, but this is a good starting point.
This code partially gets up through the romstage just before training
memory on a Haswell reference board.
Change-Id: If572d6c21ca051b486b82a924ca0ffe05c4d0ad4
Signed-off-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-on: http://review.coreboot.org/2616
Tested-by: build bot (Jenkins)
Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
Diffstat (limited to 'src/cpu/x86/smm/smmhandler_tseg.S')
| -rw-r--r-- | src/cpu/x86/smm/smmhandler_tseg.S | 3 |
1 files changed, 3 insertions, 0 deletions
diff --git a/src/cpu/x86/smm/smmhandler_tseg.S b/src/cpu/x86/smm/smmhandler_tseg.S index c61a611757..eb5d63ca8f 100644 --- a/src/cpu/x86/smm/smmhandler_tseg.S +++ b/src/cpu/x86/smm/smmhandler_tseg.S @@ -60,6 +60,9 @@ #if CONFIG_NORTHBRIDGE_INTEL_SANDYBRIDGE || CONFIG_NORTHBRIDGE_INTEL_IVYBRIDGE #include <northbridge/intel/sandybridge/sandybridge.h> #define TSEG_BAR (DEFAULT_PCIEXBAR | TSEG) +#elif CONFIG_NORTHBRIDGE_INTEL_HASWELL +#include <northbridge/intel/haswell/haswell.h> +#define TSEG_BAR (DEFAULT_PCIEXBAR | TSEG) #else #error "Northbridge must define TSEG_BAR." #endif |