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authorElyes HAOUAS <ehaouas@noos.fr>2018-10-24 15:55:53 +0200
committerPatrick Georgi <pgeorgi@google.com>2018-11-08 11:35:26 +0000
commita9473ecbb142d07e95b120dbab6e9e50017f1e55 (patch)
treeeff72fa0a3176aee0b2568b627553788922c7042 /src/cpu/x86/smm/smmhandler.S
parentf33e835a064d11179c37d2c306ba024aa3a636fd (diff)
src: Replace common MSR addresses with macros
Change-Id: I9fba67be12483ea5e12ccd34c648735d409bc8b0 Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/29252 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Richard Spiegel <richard.spiegel@silverbackltd.com>
Diffstat (limited to 'src/cpu/x86/smm/smmhandler.S')
-rw-r--r--src/cpu/x86/smm/smmhandler.S6
1 files changed, 2 insertions, 4 deletions
diff --git a/src/cpu/x86/smm/smmhandler.S b/src/cpu/x86/smm/smmhandler.S
index 98d67d3c3c..0989e891e2 100644
--- a/src/cpu/x86/smm/smmhandler.S
+++ b/src/cpu/x86/smm/smmhandler.S
@@ -21,7 +21,7 @@
* to 64k if we can though.
*/
-#define LAPIC_BASE_MSR 0x1b
+#include <cpu/x86/lapic_def.h>
/*
* +--------------------------------+ 0xaffff
@@ -49,8 +49,6 @@
*
*/
-#define LAPIC_ID 0xfee00020
-
/* SMM_HANDLER_OFFSET is the 16bit offset within the ASEG
* at which smm_handler_start lives. At the moment the handler
* lives right at 0xa0000, so the offset is 0.
@@ -134,7 +132,7 @@ untampered_lapic:
movw %ax, %gs
/* Get this CPU's LAPIC ID */
- movl $LAPIC_ID, %esi
+ movl $(LOCAL_APIC_ADDR | LAPIC_ID), %esi
movl (%esi), %ecx
shr $24, %ecx