diff options
| author | Alexandru Gagniuc <mr.nuke.me@gmail.com> | 2014-04-12 21:57:18 -0500 |
|---|---|---|
| committer | Alexandru Gagniuc <mr.nuke.me@gmail.com> | 2014-04-16 23:42:00 +0200 |
| commit | 53072d869ad9234781b5a479dfcc9a9288723da6 (patch) | |
| tree | 533bb1f9cb5b97fd8d3f22d49368b47831b464f1 /src/cpu/x86/smm/smmhandler.S | |
| parent | 342ac64a5d6f5ab639fb140ae69f9b3597878cba (diff) | |
cpu/amd/agesa/family15tn: Add initial support for SMM mode
This is the minimal setup needed to be able to execute SMI handlers.
Only support for ASEG handlers is added, which should be sufficient
for Trinity (up to 4 cores).
There are a few hacks which need to be introduced in generic code in
order to make this work properly, but these hacks are self-contained.
They are a not a result of any special needs of this CPU, but rather
from a poorly designed infrastructure. Comments are added to explain
how such code could be refactored in the future.
Change-Id: Iefd4ae17cf0206cae8848cadba3a12cbe3b2f8b6
Signed-off-by: Alexandru Gagniuc <mr.nuke.me@gmail.com>
Reviewed-on: http://review.coreboot.org/5493
Tested-by: build bot (Jenkins)
Reviewed-by: Aaron Durbin <adurbin@gmail.com>
Diffstat (limited to 'src/cpu/x86/smm/smmhandler.S')
| -rw-r--r-- | src/cpu/x86/smm/smmhandler.S | 8 |
1 files changed, 8 insertions, 0 deletions
diff --git a/src/cpu/x86/smm/smmhandler.S b/src/cpu/x86/smm/smmhandler.S index 774088e1f2..484b643017 100644 --- a/src/cpu/x86/smm/smmhandler.S +++ b/src/cpu/x86/smm/smmhandler.S @@ -105,6 +105,14 @@ smm_handler_start: movl (%esi), %ecx shr $24, %ecx + /* This is an ugly hack, and we should find a way to read the CPU index + * without relying on the LAPIC ID. + */ +#if IS_ENABLED(CONFIG_CPU_AMD_AGESA_FAMILY15_TN) + /* LAPIC IDs start from 0x10; map that to the proper core index */ + subl $0x10, %ecx +#endif + /* calculate stack offset by multiplying the APIC ID * by 1024 (0x400), and save that offset in ebp. */ |