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authorAaron Durbin <adurbin@chromium.org>2017-06-16 15:16:13 -0500
committerMartin Roth <martinroth@google.com>2017-06-27 16:14:15 +0000
commit8ade68a2701603785d4acefc02ce3d7482b6beff (patch)
tree60692857eb1ac3a0d035011c2de4ce890ff5894f /src/cpu/x86/sipi_vector.S
parent604f69868ffc47c4cfc7623c83ccff89a0afcee8 (diff)
cpu/x86/smm: allow SSE instructions in SMM modules
If SSE instructions are enabled in the build assume the SMM modules are compiled with SSE instructions. As such enable the SSE instructions in SMM mode by setting up the cr4 register. In addition, provide a place to save and restore the SSE state in both the relocation handler and permanent handler. Change-Id: Ifa16876b57544919fde88fba5b8f18e4ca286841 Signed-off-by: Aaron Durbin <adurbin@chromium.org> Reviewed-on: https://review.coreboot.org/20244 Reviewed-by: Furquan Shaikh <furquan@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Diffstat (limited to 'src/cpu/x86/sipi_vector.S')
-rw-r--r--src/cpu/x86/sipi_vector.S7
1 files changed, 7 insertions, 0 deletions
diff --git a/src/cpu/x86/sipi_vector.S b/src/cpu/x86/sipi_vector.S
index 1c5120763e..e65491507e 100644
--- a/src/cpu/x86/sipi_vector.S
+++ b/src/cpu/x86/sipi_vector.S
@@ -185,6 +185,13 @@ load_msr:
and $~(CR0_CLEAR_FLAGS_CACHE_ENABLE), %eax
mov %eax, %cr0
+#if IS_ENABLED(CONFIG_SSE)
+ /* Enable sse instructions. */
+ mov %cr4, %eax
+ orl $(CR4_OSFXSR | CR4_OSXMMEXCPT), %eax
+ mov %eax, %cr4
+#endif
+
/* c_handler(cpu_num) */
push %esi /* cpu_num */
mov c_handler, %eax