diff options
| author | Marshall Dawson <marshalldawson3rd@gmail.com> | 2017-10-19 09:45:16 -0600 |
|---|---|---|
| committer | Aaron Durbin <adurbin@chromium.org> | 2018-02-16 22:38:50 +0000 |
| commit | c0dbedac431a2038cd7382d4c0cd8ccb958675ac (patch) | |
| tree | 646e35c9c9076a54be405082a29205fd72198f5c /src/cpu/x86/sipi_vector.S | |
| parent | ed089376e39b85af61b8db6904627d294f31c55b (diff) | |
x86/mtrr: Enable Rd/WrDram mod in AMD fixed MTRRs
AMD's fixed MTRRs have RdDram and WrDram bits that route memory
accesses to DRAM vs. MMIO. These are typically hidden for normal
operation by clearing SYS_CFG[19] (MtrrFixDramModEn). According to
BKDGs and AMD64 Programmer's Manual vol 2, this bit is clear at
reset, should be set for configuration during POST, then cleared for
normal operation.
Attempting to modify the RdDram and WrDram settings without unhiding
them causes a General Protection Fault. Add functions to enable and
disable MtrrFixDramModEn. Unhide/hide as necessary when copying or
writing the fixed MTRRs.
Finally, modify sipi_vector.S to enable the bits prior to writing
the fixed MTRRs and disable when complete.
This functionality is compiled out on non-AMD platforms.
BUG=b:68019051
TEST=Boot Kahlee, check steps with HDT
Change-Id: Ie195131ff752400eb886dfccc39b314b4fa6b3f3
Signed-off-by: Marshall Dawson <marshalldawson3rd@gmail.com>
Reviewed-on: https://review.coreboot.org/23722
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Diffstat (limited to 'src/cpu/x86/sipi_vector.S')
| -rw-r--r-- | src/cpu/x86/sipi_vector.S | 17 |
1 files changed, 17 insertions, 0 deletions
diff --git a/src/cpu/x86/sipi_vector.S b/src/cpu/x86/sipi_vector.S index bd60c65a88..83606bd920 100644 --- a/src/cpu/x86/sipi_vector.S +++ b/src/cpu/x86/sipi_vector.S @@ -15,6 +15,7 @@ */ #include <cpu/x86/cr.h> +#include <cpu/amd/mtrr.h> /* The SIPI vector is responsible for initializing the APs in the sytem. It * loads microcode, sets up MSRs, and enables caching before calling into @@ -172,6 +173,15 @@ microcode_done: mov msr_count, %ebx test %ebx, %ebx jz 1f + +#if IS_ENABLED(CONFIG_X86_AMD_FIXED_MTRRS) + /* Allow modification of RdDram and WrDram bits */ + mov $SYSCFG_MSR, %ecx + rdmsr + or $SYSCFG_MSR_MtrrFixDramModEn, %eax + wrmsr +#endif + load_msr: mov (%edi), %ecx mov 4(%edi), %eax @@ -181,6 +191,13 @@ load_msr: dec %ebx jnz load_msr +#if IS_ENABLED(CONFIG_X86_AMD_FIXED_MTRRS) + mov $SYSCFG_MSR, %ecx + rdmsr + and $~SYSCFG_MSR_MtrrFixDramModEn, %eax + wrmsr +#endif + 1: /* Enable caching. */ mov %cr0, %eax |