summaryrefslogtreecommitdiff
path: root/src/cpu/x86/mtrr
diff options
context:
space:
mode:
authorFelix Held <felix-coreboot@felixheld.de>2023-09-19 18:06:00 +0200
committerFelix Held <felix-coreboot@felixheld.de>2023-09-20 18:18:01 +0000
commit8d8ed454dbc284bedb6a7bb7dfa7b2ade166b23c (patch)
treeb2a34fe65b7d436515123a41039a5befa39e0780 /src/cpu/x86/mtrr
parent45343719c1be8e557156c8636f4baef3215cd133 (diff)
cpu/x86/mtrr/debug: use MTRR_PHYS_MASK
Instead adding 1 to the result of MTRR_PHYS_BASE(index) to get the variable MTRR's mask MSR number, use the MTRR_PHYS_MASK macro. Signed-off-by: Felix Held <felix-coreboot@felixheld.de> Change-Id: Ieecc57feb25afa83f3a53384e5a286f2e4e82093 Reviewed-on: https://review.coreboot.org/c/coreboot/+/78006 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Matt DeVillier <matt.devillier@amd.corp-partner.google.com>
Diffstat (limited to 'src/cpu/x86/mtrr')
-rw-r--r--src/cpu/x86/mtrr/debug.c5
1 files changed, 2 insertions, 3 deletions
diff --git a/src/cpu/x86/mtrr/debug.c b/src/cpu/x86/mtrr/debug.c
index 0f20a32c1d..ffaa2a1bb2 100644
--- a/src/cpu/x86/mtrr/debug.c
+++ b/src/cpu/x86/mtrr/debug.c
@@ -98,12 +98,11 @@ static void display_mtrr_def_type(void)
static void display_variable_mtrr(int index, uint64_t address_mask)
{
- const uint32_t msr_reg = MTRR_PHYS_BASE(index);
uint64_t base_address;
uint64_t length;
uint64_t mask;
- const msr_t msr_a = rdmsr(msr_reg);
- const msr_t msr_m = rdmsr(msr_reg + 1);
+ const msr_t msr_a = rdmsr(MTRR_PHYS_BASE(index));
+ const msr_t msr_m = rdmsr(MTRR_PHYS_MASK(index));
if (msr_m.raw & MTRR_PHYS_MASK_VALID) {
base_address = (msr_a.raw & 0xfffffffffffff000ULL)