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authorFelix Held <felix-coreboot@felixheld.de>2020-08-28 02:12:06 +0200
committerPatrick Georgi <pgeorgi@google.com>2020-08-31 06:42:49 +0000
commit764b987a6f93a64f18b1557e1591fc2afe47110c (patch)
treee97eebd3199373d82bfeaaa53747a1d21d49c613 /src/cpu/x86/mtrr
parent82a0a63f99a7c9e9afaf7fc6b85a93ef75e480cf (diff)
mb/google/zork/trembyle: add PCIe GPP clock setting to devicetree
BUG=b:149970243 BRANCH=zork Change-Id: Ie3fc83484c6ce769956dc8e6e57194ffebb4f5b0 Signed-off-by: Felix Held <felix-coreboot@felixheld.de> Reviewed-on: https://review.coreboot.org/c/coreboot/+/44890 Reviewed-by: Aaron Durbin <adurbin@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Diffstat (limited to 'src/cpu/x86/mtrr')
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