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authorMichael Niewöhner <foss@mniewoehner.de>2020-11-12 23:50:37 +0100
committerMichael Niewöhner <foss@mniewoehner.de>2020-11-14 18:54:35 +0000
commitc66e1c2a319a682a4616589901df301a816076ae (patch)
tree9d05943ffb743a0a31f15e65c60efe6ab52d6481 /src/cpu/x86/mtrr
parented21df6cec49f2c7dd5ae8286eaee958104e781d (diff)
soc/intel/cnl: enable ACPI CPPC entries generation
Enable CPPC entries generation, needed for Intel SpeedShift. Test: dumped SSDT from Clevo L140CU and checked decompiled version Change-Id: I0c8066a31d3bec27776836aac54c335c0e5d74e6 Signed-off-by: Michael Niewöhner <foss@mniewoehner.de> Reviewed-on: https://review.coreboot.org/c/coreboot/+/47541 Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Diffstat (limited to 'src/cpu/x86/mtrr')
0 files changed, 0 insertions, 0 deletions