Remove CACHE_ROM.

With the recent improvement 3d6ffe76f8a505c2dff5d5c6146da3d63dad6e82,
speedup by CACHE_ROM is reduced a lot.
On the other hand this makes coreboot run out of MTRRs depending on
system configuration, hence screwing up I/O access and cache
coherency in worst cases.

CACHE_ROM requires the user to sanity check their boot output because
the feature is brittle. The working configuration is dependent on I/O
hole size, ram size, and chipset. Because of this the current
implementation can leave a system configured in an inconsistent state
leading to unexpected results such as poor performance and/or
inconsistent cache-coherency

Remove this as a buggy feature until we figure out how to do it properly
if necessary.

Change-Id: I858d78a907bf042fcc21fdf7a2bf899e9f6b591d
Signed-off-by: Vladimir Serbinenko <phcoder@gmail.com>
Reviewed-on: http://review.coreboot.org/5146
Tested-by: build bot (Jenkins)
Reviewed-by: Aaron Durbin <adurbin@google.com>

1 files changed, 0 insertions, 76 deletions

diff --git a/src/cpu/x86/mtrr/mtrr.c b/src/cpu/x86/mtrr/mtrr.c
index d85a86982c..86e31d0010 100644
--- a/src/cpu/x86/mtrr/mtrr.c
+++ b/src/cpu/x86/mtrr/mtrr.c
@@ -199,16 +199,6 @@ static struct memranges *get_physical_address_space(void)
 		memranges_add_resources_filter(addr_space, mask, match, MTRR_TYPE_WRCOMB,
 		                               filter_vga_wrcomb);
 
-#if CONFIG_CACHE_ROM
-		/* Add a write-protect region covering the ROM size
-		 * when CONFIG_CACHE_ROM is enabled. The ROM is assumed
-		 * to be located at 4GiB - rom size. */
-		resource_t rom_base = RANGE_TO_PHYS_ADDR(
-			RANGE_4GB - PHYS_TO_RANGE_ADDR(CACHE_ROM_SIZE));
-		memranges_insert(addr_space, rom_base, CACHE_ROM_SIZE,
-		                 MTRR_TYPE_WRPROT);
-#endif
-
 		/* The address space below 4GiB is special. It needs to be
 		 * covered entirly by range entries so that MTRR calculations
 		 * can be properly done for the full 32-bit address space.
@@ -380,61 +370,6 @@ void x86_setup_fixed_mtrrs(void)
 	enable_fixed_mtrr();
 }
 
-/* Keep track of the MTRR that covers the ROM for caching purposes. */
-#if CONFIG_CACHE_ROM
-static long rom_cache_mtrr = -1;
-
-long x86_mtrr_rom_cache_var_index(void)
-{
-	return rom_cache_mtrr;
-}
-
-void x86_mtrr_enable_rom_caching(void)
-{
-	msr_t msr_val;
-	unsigned long index;
-
-	if (rom_cache_mtrr < 0)
-		return;
-
-	index = rom_cache_mtrr;
-	disable_cache();
-	msr_val = rdmsr(MTRRphysBase_MSR(index));
-	msr_val.lo &= ~0xff;
-	msr_val.lo |= MTRR_TYPE_WRPROT;
-	wrmsr(MTRRphysBase_MSR(index), msr_val);
-	enable_cache();
-}
-
-void x86_mtrr_disable_rom_caching(void)
-{
-	msr_t msr_val;
-	unsigned long index;
-
-	if (rom_cache_mtrr < 0)
-		return;
-
-	index = rom_cache_mtrr;
-	disable_cache();
-	msr_val = rdmsr(MTRRphysBase_MSR(index));
-	msr_val.lo &= ~0xff;
-	wrmsr(MTRRphysBase_MSR(index), msr_val);
-	enable_cache();
-}
-
-static void disable_cache_rom(void *unused)
-{
-	x86_mtrr_disable_rom_caching();
-}
-
-BOOT_STATE_INIT_ENTRIES(disable_rom_cache_bscb) = {
-	BOOT_STATE_INIT_ENTRY(BS_OS_RESUME, BS_ON_ENTRY,
-	                      disable_cache_rom, NULL),
-	BOOT_STATE_INIT_ENTRY(BS_PAYLOAD_LOAD, BS_ON_EXIT,
-	                      disable_cache_rom, NULL),
-};
-#endif
-
 struct var_mtrr_state {
 	struct memranges *addr_space;
 	int above4gb;
@@ -482,17 +417,6 @@ static void write_var_mtrr(struct var_mtrr_state *var_state,
 	mask = (1ULL << var_state->address_bits) - 1;
 	rsize = rsize & mask;
 
-#if CONFIG_CACHE_ROM
-	/* CONFIG_CACHE_ROM allocates an MTRR specifically for allowing
-	 * one to turn on caching for faster ROM access. However, it is
-	 * left to the MTRR callers to enable it. */
-	if (mtrr_type == MTRR_TYPE_WRPROT) {
-		mtrr_type = MTRR_TYPE_UNCACHEABLE;
-		if (rom_cache_mtrr < 0)
-			rom_cache_mtrr = var_state->mtrr_index;
-	}
-#endif
-
 	printk(BIOS_DEBUG, "MTRR: %d base 0x%016llx mask 0x%016llx type %d\n",
 	       var_state->mtrr_index, rbase, rsize, mtrr_type);