diff options
| author | Subrata Banik <subratabanik@google.com> | 2024-03-18 17:10:57 +0530 |
|---|---|---|
| committer | Subrata Banik <subratabanik@google.com> | 2024-03-19 13:02:04 +0000 |
| commit | 194128a3af2c954cbdb496b6bada99208029bb73 (patch) | |
| tree | 6896a7cb0810a45eed63d27d30d18affac054550 /src/cpu/x86/mtrr/earlymtrr.c | |
| parent | 85e3fe12ed8df97c6a2e2d76d1db9f7cbde52d9a (diff) | |
cpu/x86/mtrr: Error out caching limitation during NEM
Improves user experience by highlighting a possibility of runtime
hangs caused by unsupported WB caching during NEM.
Recently we have encountered an issue on Intel platform and came to
know about the NEM logical limitation where due to cache sets are not
in power_on_two running into a runtime hang upon enabling WB caching.
BUG=b:306677879
BRANCH=firmware-rex-15709.B
TEST=Verified boot on google/ovis and google/rex (including Ovis with
non-power-of-two cache configuration).
Change-Id: Ic4fbef1fcc018856420428139683897634c9f85d
Signed-off-by: Subrata Banik <subratabanik@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/81336
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Jérémy Compostella <jeremy.compostella@intel.com>
Diffstat (limited to 'src/cpu/x86/mtrr/earlymtrr.c')
| -rw-r--r-- | src/cpu/x86/mtrr/earlymtrr.c | 3 |
1 files changed, 3 insertions, 0 deletions
diff --git a/src/cpu/x86/mtrr/earlymtrr.c b/src/cpu/x86/mtrr/earlymtrr.c index b6cc73751d..a55b2dcc98 100644 --- a/src/cpu/x86/mtrr/earlymtrr.c +++ b/src/cpu/x86/mtrr/earlymtrr.c @@ -37,6 +37,9 @@ void set_var_mtrr( /* FIXME: It only support 4G less range */ msr_t basem, maskm; + if (type == MTRR_TYPE_WRBACK && !is_cache_sets_power_of_two() && ENV_CACHE_AS_RAM) + printk(BIOS_ERR, "MTRR Error: Type %x may not be supported due to NEM limitation\n", + type); if (!IS_POWER_OF_2(size)) printk(BIOS_ERR, "MTRR Error: size %#x is not a power of two\n", size); if (size < 4 * KiB) |