diff options
| author | Martin Roth <martinroth@google.com> | 2018-01-10 16:56:04 -0800 |
|---|---|---|
| committer | Martin Roth <martinroth@google.com> | 2018-01-12 00:57:00 +0000 |
| commit | 3441292ecda5e76a98ff63f55fc45d010fc76188 (patch) | |
| tree | 2ecf436040cbd04d7c06243dbdf7455376843e84 /src/cpu/x86/mp_init.c | |
| parent | 6719862de80cec31a910ab1cc39fb7d3ba7b9a80 (diff) | |
mainboard/google/kahlee: Enable PCIe Lane 2
The Port initializer had been changed from PortDisabled to PortEnabled,
but engine inializer hadn't been updated from PcieUnusedEngine to
PciePortEngine. Update this so the port works.
Also change disabled port to PcieUnusedEngine.
BUG=b:71818026
TEST=PCIe device now shows up on D2F4
Change-Id: I11eb8c1fbad12fa9cf34d758a4ef3c22ef8ba4f7
Signed-off-by: Martin Roth <martinroth@google.com>
Reviewed-on: https://review.coreboot.org/23210
Reviewed-by: Daniel Kurtz <djkurtz@google.com>
Reviewed-by: Chris Ching <chingcodes@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Diffstat (limited to 'src/cpu/x86/mp_init.c')
0 files changed, 0 insertions, 0 deletions