diff options
| author | Myles Watson <mylesgw@gmail.com> | 2009-02-09 17:52:54 +0000 |
|---|---|---|
| committer | Myles Watson <mylesgw@gmail.com> | 2009-02-09 17:52:54 +0000 |
| commit | c4ddbff70621449606fa3f0a1ad8277fac0f5aeb (patch) | |
| tree | 603222e5e54f62b47219b1477efc4bfccf8a65fa /src/cpu/x86/lapic | |
| parent | 4505948faec7cc30edb9daebf53ca006d4a1645a (diff) | |
Remove some warnings, mainly from format strings which didn't match the
arguments.
Signed-off-by: Myles Watson <mylesgw@gmail.com>
Acked-by: Peter Stuge <peter@stuge.se>
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@3931 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
Diffstat (limited to 'src/cpu/x86/lapic')
| -rw-r--r-- | src/cpu/x86/lapic/lapic.c | 2 | ||||
| -rw-r--r-- | src/cpu/x86/lapic/lapic_cpu_init.c | 10 |
2 files changed, 5 insertions, 7 deletions
diff --git a/src/cpu/x86/lapic/lapic.c b/src/cpu/x86/lapic/lapic.c index 8c111e8d71..fc736c96d2 100644 --- a/src/cpu/x86/lapic/lapic.c +++ b/src/cpu/x86/lapic/lapic.c @@ -55,7 +55,7 @@ void setup_lapic(void) LAPIC_DELIVERY_MODE_NMI) ); - printk_debug(" apic_id: 0x%02x ", lapicid()); + printk_debug(" apic_id: 0x%02lx ", lapicid()); #else /* !NEED_LLAPIC */ /* Only Pentium Pro and later have those MSR stuff */ diff --git a/src/cpu/x86/lapic/lapic_cpu_init.c b/src/cpu/x86/lapic/lapic_cpu_init.c index 0fd31d0382..4a879c561a 100644 --- a/src/cpu/x86/lapic/lapic_cpu_init.c +++ b/src/cpu/x86/lapic/lapic_cpu_init.c @@ -85,14 +85,14 @@ static int lapic_start_cpu(unsigned long apicid) send_status = lapic_read(LAPIC_ICR) & LAPIC_ICR_BUSY; } while (send_status && (timeout++ < 1000)); if (timeout >= 1000) { - printk_err("CPU %d: First apic write timed out. Disabling\n", + printk_err("CPU %ld: First apic write timed out. Disabling\n", apicid); // too bad. - printk_err("ESR is 0x%x\n", lapic_read(LAPIC_ESR)); + printk_err("ESR is 0x%lx\n", lapic_read(LAPIC_ESR)); if (lapic_read(LAPIC_ESR)) { printk_err("Try to reset ESR\n"); lapic_write_around(LAPIC_ESR, 0); - printk_err("ESR is 0x%x\n", lapic_read(LAPIC_ESR)); + printk_err("ESR is 0x%lx\n", lapic_read(LAPIC_ESR)); } return 0; } @@ -114,7 +114,7 @@ static int lapic_start_cpu(unsigned long apicid) send_status = lapic_read(LAPIC_ICR) & LAPIC_ICR_BUSY; } while (send_status && (timeout++ < 1000)); if (timeout >= 1000) { - printk_err("CPU %d: Second apic write timed out. Disabling\n", + printk_err("CPU %ld: Second apic write timed out. Disabling\n", apicid); // too bad. return 0; @@ -345,8 +345,6 @@ void stop_this_cpu(void) /* C entry point of secondary cpus */ void secondary_cpu_init(void) { - unsigned long cpunum; - atomic_inc(&active_cpus); #if SERIAL_CPU_INIT == 1 #if CONFIG_MAX_CPUS>2 |