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authorJeremy Compostella <jeremy.compostella@intel.com>2023-05-22 17:38:10 -0700
committerMartin L Roth <gaumless@gmail.com>2023-05-31 14:22:31 +0000
commit4a2ce029fb9af7aaa33128ae0af2d4a01dfadd08 (patch)
tree1adf753382cd3648fe1b4677247c6f0ec99df876 /src/cpu/x86/cache
parentf167df4d3fbfd74b4bbf35502daf8e533a925eaf (diff)
cpu/x86/mp_init: Use clflush to write SIPI data back to RAM
Improve boot time performances by replacing the wbinvd instruction with multiple clflush to ensure that the SIPI data is written back to RAM. According to some experimental measurements, the wbinvd execution takes between 1.6 up and 6 milliseconds to complete. In the case of the SIPI data, wbinvd unnecessarily flushes and invalidates the entire cache. Indeed, the SIPI module is quite small (about 400 bytes) and cflush'ing the associated cache lines is almost instantaneous, typically less than 100 microseconds. BUG=b/260455826 TEST=Successful boot on Skolas and Rex board Change-Id: I0e00db8eaa6a3cb41bec3422572c8f2a9bec4057 Signed-off-by: Jeremy Compostella <jeremy.compostella@intel.com> Suggested-by: Erin Park <erin.park@intel.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/75391 Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
Diffstat (limited to 'src/cpu/x86/cache')
-rw-r--r--src/cpu/x86/cache/cache.c12
1 files changed, 5 insertions, 7 deletions
diff --git a/src/cpu/x86/cache/cache.c b/src/cpu/x86/cache/cache.c
index d02d6d4427..6413660b83 100644
--- a/src/cpu/x86/cache/cache.c
+++ b/src/cpu/x86/cache/cache.c
@@ -12,16 +12,11 @@ bool clflush_supported(void)
return (cpuid_edx(1) >> CPUID_FEATURE_CLFLUSH_BIT) & 1;
}
-static void clflush_region(const uintptr_t start, const size_t size)
+void clflush_region(const uintptr_t start, const size_t size)
{
uintptr_t addr;
const size_t cl_size = ((cpuid_ebx(1) >> 8) & 0xff) * 8;
- if (!clflush_supported()) {
- printk(BIOS_DEBUG, "Not flushing cache to RAM, CLFLUSH not supported\n");
- return;
- }
-
printk(BIOS_SPEW, "CLFLUSH [0x%lx, 0x%lx]\n", start, start + size);
for (addr = ALIGN_DOWN(start, cl_size); addr < start + size; addr += cl_size)
@@ -54,5 +49,8 @@ void arch_segment_loaded(uintptr_t start, size_t size, int flags)
if (!cbmem_online())
return;
- clflush_region(start, size);
+ if (clflush_supported())
+ clflush_region(start, size);
+ else
+ printk(BIOS_DEBUG, "Not flushing cache to RAM, CLFLUSH not supported\n");
}