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| author | Arthur Heymans <arthur@aheymans.xyz> | 2021-05-29 08:10:49 +0200 |
|---|---|---|
| committer | Felix Held <felix-coreboot@felixheld.de> | 2023-11-09 13:20:18 +0000 |
| commit | a2bc2540c2d004b475b401ccf0b162c2452857bb (patch) | |
| tree | 902284670b43d9e06d7dccc64dbeec24073fca4e /src/cpu/x86/cache/cache.c | |
| parent | 4ce52f622ed7fbac4bf5545fd7d39256203cdefe (diff) | |
Allow to build romstage sources inside the bootblock
Having a separate romstage is only desirable:
- with advanced setups like vboot or normal/fallback
- boot medium is slow at startup (some ARM SOCs)
- bootblock is limited in size (Intel APL 32K)
When this is not the case there is no need for the extra complexity
that romstage brings. Including the romstage sources inside the
bootblock substantially reduces the total code footprint. Often the
resulting code is 10-20k smaller.
This is controlled via a Kconfig option.
TESTED: works on qemu x86, arm and aarch64 with and without VBOOT.
Change-Id: Id68390edc1ba228b121cca89b80c64a92553e284
Signed-off-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/55068
Reviewed-by: Julius Werner <jwerner@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
Diffstat (limited to 'src/cpu/x86/cache/cache.c')
| -rw-r--r-- | src/cpu/x86/cache/cache.c | 2 |
1 files changed, 1 insertions, 1 deletions
diff --git a/src/cpu/x86/cache/cache.c b/src/cpu/x86/cache/cache.c index 6413660b83..11524e65db 100644 --- a/src/cpu/x86/cache/cache.c +++ b/src/cpu/x86/cache/cache.c @@ -33,7 +33,7 @@ void arch_segment_loaded(uintptr_t start, size_t size, int flags) to make sure that our code hits dram during romstage. */ if (!ENV_CACHE_AS_RAM) return; - if (!ENV_ROMSTAGE) + if (!ENV_RAMINIT) return; if (!CONFIG(POSTCAR_STAGE)) return; |