amd/mct/ddr3: Correctly program maximum read latency

The existing code inadvertently calculated the maximum read
latency for nonexistent channel 2 instead of for channels
0 and 1 as intended.  Fix the calls to the maximum read latency
training function.

Found-by: Coverity Scan #1347354
Change-Id: If34b204ac73cd20859102cc3b2f40bc99c2ce471
Signed-off-by: Timothy Pearson <tpearson@raptorengineering.com>
Reviewed-on: https://review.coreboot.org/18072
Tested-by: build bot (Jenkins)
Reviewed-by: Martin Roth <martinroth@google.com>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Tested-by: Raptor Engineering Automated Test Stand <noreply@raptorengineeringinc.com>

0 files changed, 0 insertions, 0 deletions