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authorAaron Durbin <adurbin@chromium.org>2013-10-21 12:15:29 -0500
committerAaron Durbin <adurbin@google.com>2014-01-30 06:05:02 +0100
commite0785c03310574dcd96d5bbe878a1bae8c0f2a8c (patch)
treea4165248a68b0835d38cb4dd723fa39641aa8862 /src/cpu/x86/Kconfig
parent75e297428f6a88406fa3e1c0b54ab3d4f411db5c (diff)
x86: parallel MP initialization
Provide a common entry point for bringing up the APs in parallel. This work is based off of the Haswell one which can be moved over to this in the future. The APs are brought up and have the BSP's MTRRs duplicated in their own MTRRs. Additionally, Microcode is loaded before enabling caching. However, the current microcode loading support assumes Intel's mechanism. The infrastructure provides a notion of a flight plan for the BSP and APs. This allows for flexibility in the order of operations for a given architecture/chip without providing any specific policy. Therefore, the chipset caller can provide the order that is required. BUG=chrome-os-partner:22862 BRANCH=None TEST=Built and booted on rambi with baytrail specific patches. Change-Id: I0539047a1b24c13ef278695737cdba3b9344c820 Signed-off-by: Aaron Durbin <adurbin@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/173703 Reviewed-on: http://review.coreboot.org/4888 Reviewed-by: Alexandru Gagniuc <mr.nuke.me@gmail.com> Tested-by: build bot (Jenkins)
Diffstat (limited to 'src/cpu/x86/Kconfig')
-rw-r--r--src/cpu/x86/Kconfig7
1 files changed, 7 insertions, 0 deletions
diff --git a/src/cpu/x86/Kconfig b/src/cpu/x86/Kconfig
index c64a8e477b..21282c321a 100644
--- a/src/cpu/x86/Kconfig
+++ b/src/cpu/x86/Kconfig
@@ -115,3 +115,10 @@ config X86_AMD_FIXED_MTRRS
help
This option informs the MTRR code to use the RdMem and WrMem fields
in the fixed MTRR MSRs.
+
+config PARALLEL_MP
+ def_bool n
+ help
+ This option uses common MP infrastructure for bringing up APs
+ in parallel. It additionally provides a more flexible mechanism
+ for sequencing the steps of bringing up the APs.