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| author | Nico Huber <nico.h@gmx.de> | 2024-05-31 17:17:00 +0200 |
|---|---|---|
| committer | Lean Sheng Tan <sheng.tan@9elements.com> | 2024-11-11 09:16:55 +0000 |
| commit | 003d6397c6237e618e846b655283bdb9c605c518 (patch) | |
| tree | e423a541cc0c5c21ef3a2021373b07629cb13b7f /src/cpu/via | |
| parent | 5b0dc2b6a015288fa22803a5e2dc99c3dbc21c5c (diff) | |
via: Start template for VIA C7 w/ CX700 northbridge
The first steps to bring C7 and CX700 support back mainline. Most is
skeleton copied from the `min86' example.
The romstage entry is placed in the northbridge code, as that's where
we'll perform raminit. Support to read the FSB frequency is added right
away, same for a reset function (using CF9 reset), as both are required
for a minimal build test.
A mainboard VIA EPIA-EX is also introduced for build testing, and in
later stages boot testing as well.
Links:
DS: https://theretroweb.com/chip/documentation/via-cx700-datasheet-feb06-666c8b172d347554179891.pdf
PM: https://web.archive.org/web/20180616220857/http://linux.via.com.tw/support/beginDownload.action?eleid=141&fid=221
Change-Id: I66f678fae0d5a27bb09c0c6c702440900998e574
Signed-off-by: Nico Huber <nico.h@gmx.de>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/82765
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Diffstat (limited to 'src/cpu/via')
| -rw-r--r-- | src/cpu/via/Kconfig | 1 | ||||
| -rw-r--r-- | src/cpu/via/Makefile.mk | 3 | ||||
| -rw-r--r-- | src/cpu/via/c7/Kconfig | 17 | ||||
| -rw-r--r-- | src/cpu/via/c7/Makefile.mk | 6 | ||||
| -rw-r--r-- | src/cpu/via/car/cache_as_ram.S | 13 | ||||
| -rw-r--r-- | src/cpu/via/car/exit_car.S | 8 |
6 files changed, 48 insertions, 0 deletions
diff --git a/src/cpu/via/Kconfig b/src/cpu/via/Kconfig new file mode 100644 index 0000000000..20f7c95a16 --- /dev/null +++ b/src/cpu/via/Kconfig @@ -0,0 +1 @@ +source "src/cpu/via/*/Kconfig" diff --git a/src/cpu/via/Makefile.mk b/src/cpu/via/Makefile.mk new file mode 100644 index 0000000000..e8b7820bdf --- /dev/null +++ b/src/cpu/via/Makefile.mk @@ -0,0 +1,3 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +subdirs-$(CONFIG_CPU_VIA_C7) += c7 diff --git a/src/cpu/via/c7/Kconfig b/src/cpu/via/c7/Kconfig new file mode 100644 index 0000000000..df81b3f84e --- /dev/null +++ b/src/cpu/via/c7/Kconfig @@ -0,0 +1,17 @@ +## SPDX-License-Identifier: GPL-2.0-only + +config CPU_VIA_C7 + bool + select ARCH_X86 + select NO_SMM + select SSE2 + select UNKNOWN_TSC_RATE + select UDELAY_LAPIC + select LAPIC_MONOTONIC_TIMER + +if CPU_VIA_C7 + +config DCACHE_BSP_STACK_SIZE + default 0x1000 + +endif diff --git a/src/cpu/via/c7/Makefile.mk b/src/cpu/via/c7/Makefile.mk new file mode 100644 index 0000000000..0890cee18b --- /dev/null +++ b/src/cpu/via/c7/Makefile.mk @@ -0,0 +1,6 @@ +## SPDX-License-Identifier: GPL-2.0-only + +bootblock-y += ../car/cache_as_ram.S +bootblock-y += ../../intel/car/bootblock.c + +postcar-y += ../car/exit_car.S diff --git a/src/cpu/via/car/cache_as_ram.S b/src/cpu/via/car/cache_as_ram.S new file mode 100644 index 0000000000..5c5066d7ea --- /dev/null +++ b/src/cpu/via/car/cache_as_ram.S @@ -0,0 +1,13 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +.section .init, "ax", @progbits + +.global bootblock_pre_c_entry + +.code32 +bootblock_pre_c_entry: + call bootblock_c_entry_bist + +.Lhlt: + hlt + jmp .Lhlt diff --git a/src/cpu/via/car/exit_car.S b/src/cpu/via/car/exit_car.S new file mode 100644 index 0000000000..0f1b227c2d --- /dev/null +++ b/src/cpu/via/car/exit_car.S @@ -0,0 +1,8 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +.global chipset_teardown_car + +.code32 +chipset_teardown_car: + /* Return to caller. */ + jmp *%esp |