Add VIA CX700 support, plus VIA vt8454c reference board support.

Signed-off-by: Stefan Reinauer <stepan@coresystems.de>
Acked-by: Uwe Hermann <uwe@hermann-uwe.de>
Acked-by: Ronald G. Minnich <rminnich@gmail.com>



git-svn-id: svn://svn.coreboot.org/coreboot/trunk@4126 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

3 files changed, 116 insertions, 5 deletions

diff --git a/src/cpu/via/car/cache_as_ram_post.c b/src/cpu/via/car/cache_as_ram_post.c
new file mode 100644
index 0000000000..99e0dd89ec
--- /dev/null
+++ b/src/cpu/via/car/cache_as_ram_post.c
@@ -0,0 +1,106 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright (C) 2008 VIA Technologies, Inc.
+ * (Written by Jason Zhao <jasonzhao@viatech.com.cn> for VIA)
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; version 2 of the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA  02110-1301 USA
+ */
+ 
+        __asm__ volatile (
+	/* 
+	FIXME : backup stack in CACHE_AS_RAM into mmx and sse and after we get STACK up, we restore that.
+		It is only needed if we want to go back
+	*/
+	
+        /* We don't need cache as ram for now on */
+        /* disable cache */
+        "movl    %cr0, %eax\n\t"
+        "orl    $(0x1<<30),%eax\n\t"
+        "movl    %eax, %cr0\n\t"
+
+
+        /* Set the default memory type and disable fixed and enable variable MTRRs */
+        "movl    $0x2ff, %ecx\n\t"
+	//"movl    $MTRRdefType_MSR, %ecx\n\t"
+        "xorl    %edx, %edx\n\t"
+        /* Enable Variable and Disable Fixed MTRRs */
+        "movl    $0x00000800, %eax\n\t"
+        "wrmsr\n\t"
+
+        /* enable caching for first 1M using variable mtrr */
+        "movl    $0x200, %ecx\n\t"
+        "xorl    %edx, %edx\n\t"
+        "movl     $(0 | 6), %eax\n\t"
+	//"movl     $(0 | MTRR_TYPE_WRBACK), %eax\n\t"
+        "wrmsr\n\t"
+ 
+/*Jasonzhao@viatech.com.cn, I enable cache for 0-7ffff, 80000-9ffff, e0000-fffff;
+if 1M cacheable,then when S3 resume, there is stange color on screen for 2 sec. 
+suppose problem of a0000-dfffff and cache .
+and in x86_setup_fixed_mtrrs()(mtrr.c), 0-256M is set cacheable.*/
+
+        "movl    $0x201, %ecx\n\t"
+        "movl    $0x0000000f, %edx\n\t" /* AMD 40 bit 0xff*/
+ 	 			"movl    $((~(( 0 + 0x80000) - 1)) | 0x800), %eax\n\t"
+        "wrmsr\n\t"
+        
+        "movl    $0x202, %ecx\n\t"
+        "xorl    %edx, %edx\n\t"
+        "movl     $(0x80000 | 6), %eax\n\t"
+        "orl     $(0 | 6), %eax\n\t"
+        "wrmsr\n\t"
+
+        "movl    $0x203, %ecx\n\t"
+        "movl    $0x0000000f, %edx\n\t" /* AMD 40 bit 0xff*/
+ 	 			"movl    $((~(( 0 + 0x20000) - 1)) | 0x800), %eax\n\t"
+        "wrmsr\n\t"
+        
+        "movl    $0x204, %ecx\n\t"
+        "xorl    %edx, %edx\n\t"
+        "movl     $(0xc0000 | 6), %eax\n\t"
+        "orl     $(0 | 6), %eax\n\t"
+        "wrmsr\n\t"
+
+        "movl    $0x205, %ecx\n\t"
+        "movl    $0x0000000f, %edx\n\t" /* AMD 40 bit 0xff*/
+ 	 			"movl    $((~(( 0 + 0x40000) - 1)) | 0x800), %eax\n\t"
+        "wrmsr\n\t"        
+        
+	/*jasonzhao@viatech.com.cn add this 2008-11-27, cache XIP_ROM_BASE-SIZE to speedup the coreboot code*/
+	 			"movl    $0x206, %ecx\n\t"
+        "xorl    %edx, %edx\n\t"
+        "movl     $XIP_ROM_BASE,%eax\n\t"
+        "orl     $(0 | 6), %eax\n\t"
+        "wrmsr\n\t"
+
+	 			"movl    $0x207, %ecx\n\t"
+        "xorl    %edx, %edx\n\t"
+        "movl     $XIP_ROM_SIZE,%eax\n\t"
+        "decl	%eax\n\t"
+        "notl	%eax\n\t"
+        "orl     $(0 | 0x800), %eax\n\t"
+        "wrmsr\n\t"
+
+        /* enable cache */
+        "movl    %cr0, %eax\n\t"
+        "andl    $0x9fffffff,%eax\n\t"
+        "movl    %eax, %cr0\n\t"
+	 			"invd\n\t"
+
+	/* 
+	FIXME: I hope we don't need to change esp and ebp value here, so we can restore value from mmx sse back
+		But the problem is the range is some io related, So don't go back
+	*/
+        );
diff --git a/src/cpu/via/model_c7/Config.lb b/src/cpu/via/model_c7/Config.lb
index d956832162..a95697dd4d 100644
--- a/src/cpu/via/model_c7/Config.lb
+++ b/src/cpu/via/model_c7/Config.lb
@@ -5,8 +5,8 @@
 #
 # This program is free software; you can redistribute it and/or
 # modify it under the terms of the GNU General Public License as
-# published by the Free Software Foundation; either version 2 of
-# the License, or (at your option) any later version.
+# published by the Free Software Foundation; version 2 of
+# the License.
 #
 # This program is distributed in the hope that it will be useful,
 # but WITHOUT ANY WARRANTY; without even the implied warranty of
diff --git a/src/cpu/via/model_c7/model_c7_init.c b/src/cpu/via/model_c7/model_c7_init.c
index c32c9b5220..d9d59d1c58 100644
--- a/src/cpu/via/model_c7/model_c7_init.c
+++ b/src/cpu/via/model_c7/model_c7_init.c
@@ -1,12 +1,12 @@
 /*
  * This file is part of the coreboot project.
  * 
- * (C) 2007-2008 coresystems GmbH
+ * (C) 2007-2009 coresystems GmbH
  *
  * This program is free software; you can redistribute it and/or
  * modify it under the terms of the GNU General Public License as
- * published by the Free Software Foundation; either version 2 of
- * the License, or (at your option) any later version.
+ * published by the Free Software Foundation; version 2 of
+ * the License.
  *
  * This program is distributed in the hope that it will be useful,
  * but WITHOUT ANY WARRANTY; without even the implied warranty of
@@ -195,6 +195,11 @@ static void model_c7_init(device_t dev)
 	/* Gear up */
 	set_c7_speed(c.x86_model);
 
+	/* Enable APIC */
+	msr = rdmsr(0x1107);
+	msr.lo |= 1<<24;
+	wrmsr(0x1107, msr);
+
 	/* Turn on cache */
 	x86_enable_cache();