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| author | Duncan Laurie <dlaurie@google.com> | 2019-01-07 12:06:07 -0800 |
|---|---|---|
| committer | Duncan Laurie <dlaurie@chromium.org> | 2019-01-08 19:12:38 +0000 |
| commit | 55012d149ae3f917da419a2987081739222fc357 (patch) | |
| tree | a2a56fa045a1f92bd1ceba5da0101fea6ebc4b3a /src/cpu/via | |
| parent | 8601a16c9e6a043f424fab76c7fa12540cf2348b (diff) | |
soc/intel/cannonlake: Add FSP UPD for minimum assertion width
Expose the FSP tunables for the chipset minimum assertion width
settings which can be configured per-board.
The defaults appear to be different from what is listed in the FSP
header documentation so I tried to list what the actual default is
based on the source rather than what is stated the header comments.
Change-Id: Ie0606c2984727adf13c9fb8395586287162e49ca
Signed-off-by: Duncan Laurie <dlaurie@google.com>
Reviewed-on: https://review.coreboot.org/c/30719
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Lijian Zhao <lijian.zhao@intel.com>
Diffstat (limited to 'src/cpu/via')
0 files changed, 0 insertions, 0 deletions