cpu/x86/tsc: Flip and rename TSC_CONSTANT_RATE to UNKNOWN_TSC_RATE

The x86 timers are a bit of a mess. Cases where different stages use
different counters and timestamps use different counters from udelays.

The original intention was to only flip TSC_CONSTANT_RATE Kconfig
to NOT_CONSTANT_TSC_RATE. The name would be incorrect though, those
counters do run with a constant rate but we just lack tsc_freq_mhz()
implementation for three platforms.

Note that for boards with UNKNOWN_TSC_RATE=y, each stage will have a
slow run of calibrate_tsc_with_pit(). This is easy enough to fix with
followup implementation of tsc_freq_mhz() for the platforms.

Implementations with LAPIC_MONOTONIC_TIMER typically will not have
tsc_freq_mhz() implemented and default to UNKNOWN_TSC_RATE. However,
as they don't use TSC for udelay() the slow calibrate_tsc_with_pit()
is avoided.

Because x86/tsc_delay.tsc was using two different guards and nb/via/vx900
claimed UDELAY_TSC, but pulled UDELAY_IO implementation, we also switch
that romstage to use UDELAY_TSC.

Change-Id: I1690cb80295d6b006b75ed69edea28899b674b68
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/33928
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>

1 files changed, 1 insertions, 0 deletions

diff --git a/src/cpu/via/nano/Kconfig b/src/cpu/via/nano/Kconfig
index 4b96c7ce82..14acfd5662 100644
--- a/src/cpu/via/nano/Kconfig
+++ b/src/cpu/via/nano/Kconfig
@@ -25,6 +25,7 @@ config CPU_SPECIFIC_OPTIONS
 	select ARCH_RAMSTAGE_X86_32
 	select UDELAY_TSC
 	select TSC_MONOTONIC_TIMER
+	select UNKNOWN_TSC_RATE
 	select MMX
 	select SSE2
 	select SUPPORT_CPU_UCODE_IN_CBFS