diff options
| author | Elyes HAOUAS <ehaouas@noos.fr> | 2017-06-27 22:54:42 +0200 |
|---|---|---|
| committer | Stefan Reinauer <stefan.reinauer@coreboot.org> | 2017-06-28 00:23:32 +0000 |
| commit | 168ef399c43ad79a40a8bbb2de921a2bd906b3f5 (patch) | |
| tree | 16613245bebd7920cf3e7ce41f0d7bb5441f05e2 /src/cpu/via/nano | |
| parent | 70083a1de9e12d8dbd3ba70e7a36a7282090f0e0 (diff) | |
cpu/*: Add whitespace around '<<'
Change-Id: Id46c0b57bd7c9b954b29537c70254df947690e0b
Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr>
Reviewed-on: https://review.coreboot.org/20397
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
Diffstat (limited to 'src/cpu/via/nano')
| -rw-r--r-- | src/cpu/via/nano/nano_init.c | 12 |
1 files changed, 6 insertions, 6 deletions
diff --git a/src/cpu/via/nano/nano_init.c b/src/cpu/via/nano/nano_init.c index 3a6c1a0b02..7d6338e6ee 100644 --- a/src/cpu/via/nano/nano_init.c +++ b/src/cpu/via/nano/nano_init.c @@ -104,12 +104,12 @@ static void nano_power(void) * This MSR is not documented by VIA docs, other than setting these * bits */ msr = rdmsr(NANO_MYSTERIOUS_MSR); - msr.lo |= ( (1<<7) | (1<<4) ); + msr.lo |= ( (1 << 7) | (1 << 4) ); /* FIXME: Do we have a 6-bit or 7-bit VRM? * set bit [5] for 7-bit, or don't set it for 6 bit VRM * This will probably require a Kconfig option * My board has a 7-bit VRM, so I can't test the 6-bit VRM stuff */ - msr.lo |= (1<<5); + msr.lo |= (1 << 5); wrmsr(NANO_MYSTERIOUS_MSR, msr); /* Set the maximum frequency and voltage */ @@ -117,7 +117,7 @@ static void nano_power(void) /* Enable TM3 */ msr = rdmsr(MSR_IA32_MISC_ENABLE); - msr.lo |= ( (1<<3) | (1<<13) ); + msr.lo |= ( (1 << 3) | (1 << 13) ); wrmsr(MSR_IA32_MISC_ENABLE, msr); u8 stepping = ( cpuid_eax(0x1) ) &0xf; @@ -125,14 +125,14 @@ static void nano_power(void) /* Hello Nano 3000. The Terminator needs a CPU upgrade */ /* Enable C1e, C2e, C3e, and C4e states */ msr = rdmsr(MSR_IA32_MISC_ENABLE); - msr.lo |= ( (1<<25) | (1<<26) | (1<<31)); /* C1e, C2e, C3e */ - msr.hi |= (1<<0); /* C4e */ + msr.lo |= ( (1 << 25) | (1 << 26) | (1 << 31)); /* C1e, C2e, C3e */ + msr.hi |= (1 << 0); /* C4e */ wrmsr(MSR_IA32_MISC_ENABLE, msr); } /* Lock on Powersaver */ msr = rdmsr(MSR_IA32_MISC_ENABLE); - msr.lo |= (1<<20); + msr.lo |= (1 << 20); wrmsr(MSR_IA32_MISC_ENABLE, msr); } |