arm(64): Globally replace writel(v, a) with write32(a, v)

This patch is a raw application of the following spatch to src/:

@@
expression A, V;
@@
- writel(V, A)
+ write32(A, V)
@@
expression A, V;
@@
- writew(V, A)
+ write16(A, V)
@@
expression A, V;
@@
- writeb(V, A)
+ write8(A, V)
@@
expression A;
@@
- readl(A)
+ read32(A)
@@
expression A;
@@
- readb(A)
+ read8(A)

BRANCH=none
BUG=chromium:444723
TEST=None (depends on next patch)

Change-Id: I5dd96490c85ee2bcbc669f08bc6fff0ecc0f9e27
Signed-off-by: Patrick Georgi <pgeorgi@chromium.org>
Original-Commit-Id: 64f643da95d85954c4d4ea91c34a5c69b9b08eb6
Original-Change-Id: I366a2eb5b3a0df2279ebcce572fe814894791c42
Original-Signed-off-by: Julius Werner <jwerner@chromium.org>
Original-Reviewed-on: https://chromium-review.googlesource.com/254864
Reviewed-on: http://review.coreboot.org/9836
Tested-by: build bot (Jenkins)
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>

2 files changed, 105 insertions, 105 deletions

diff --git a/src/cpu/ti/am335x/pinmux.c b/src/cpu/ti/am335x/pinmux.c
index 292865a495..88e5ffcbf3 100644
--- a/src/cpu/ti/am335x/pinmux.c
+++ b/src/cpu/ti/am335x/pinmux.c
@@ -28,163 +28,163 @@ static struct am335x_pinmux_regs *regs =
 
 void am335x_pinmux_uart0(void)
 {
-	writel(MODE(0) | PULLUP_EN | RXACTIVE, &regs->uart0_rxd);
-	writel(MODE(0) | PULLUDEN, &regs->uart0_txd);
+	write32(&regs->uart0_rxd, MODE(0) | PULLUP_EN | RXACTIVE);
+	write32(&regs->uart0_txd, MODE(0) | PULLUDEN);
 }
 
 void am335x_pinmux_uart1(void)
 {
-	writel(MODE(0) | PULLUP_EN | RXACTIVE, &regs->uart1_rxd);
-	writel(MODE(0) | PULLUDEN, &regs->uart1_txd);
+	write32(&regs->uart1_rxd, MODE(0) | PULLUP_EN | RXACTIVE);
+	write32(&regs->uart1_txd, MODE(0) | PULLUDEN);
 }
 
 void am335x_pinmux_uart2(void)
 {
 	// UART2_RXD
-	writel(MODE(1) | PULLUP_EN | RXACTIVE, &regs->spi0_sclk);
+	write32(&regs->spi0_sclk, MODE(1) | PULLUP_EN | RXACTIVE);
 	// UART2_TXD
-	writel(MODE(1) | PULLUDEN, &regs->spi0_d0);
+	write32(&regs->spi0_d0, MODE(1) | PULLUDEN);
 }
 
 void am335x_pinmux_uart3(void)
 {
 	// UART3_RXD
-	writel(MODE(1) | PULLUP_EN | RXACTIVE, &regs->spi0_cs1);
+	write32(&regs->spi0_cs1, MODE(1) | PULLUP_EN | RXACTIVE);
 	// UART3_TXD
-	writel(MODE(1) | PULLUDEN, &regs->ecap0_in_pwm0_out);
+	write32(&regs->ecap0_in_pwm0_out, MODE(1) | PULLUDEN);
 }
 
 void am335x_pinmux_uart4(void)
 {
 	// UART4_RXD
-	writel(MODE(6) | PULLUP_EN | RXACTIVE, &regs->gpmc_wait0);
+	write32(&regs->gpmc_wait0, MODE(6) | PULLUP_EN | RXACTIVE);
 	// UART4_TXD
-	writel(MODE(6) | PULLUDEN, &regs->gpmc_wpn);
+	write32(&regs->gpmc_wpn, MODE(6) | PULLUDEN);
 }
 
 void am335x_pinmux_uart5(void)
 {
 	// UART5_RXD
-	writel(MODE(4) | PULLUP_EN | RXACTIVE, &regs->lcd_data9);
+	write32(&regs->lcd_data9, MODE(4) | PULLUP_EN | RXACTIVE);
 	// UART5_TXD
-	writel(MODE(4) | PULLUDEN, &regs->lcd_data8);
+	write32(&regs->lcd_data8, MODE(4) | PULLUDEN);
 }
 
 void am335x_pinmux_mmc0(int cd, int sk_evm)
 {
-	writel(MODE(0) | RXACTIVE | PULLUP_EN, &regs->mmc0_dat0);
-	writel(MODE(0) | RXACTIVE | PULLUP_EN, &regs->mmc0_dat1);
-	writel(MODE(0) | RXACTIVE | PULLUP_EN, &regs->mmc0_dat2);
-	writel(MODE(0) | RXACTIVE | PULLUP_EN, &regs->mmc0_dat3);
-	writel(MODE(0) | RXACTIVE | PULLUP_EN, &regs->mmc0_clk);
-	writel(MODE(0) | RXACTIVE | PULLUP_EN, &regs->mmc0_cmd);
+	write32(&regs->mmc0_dat0, MODE(0) | RXACTIVE | PULLUP_EN);
+	write32(&regs->mmc0_dat1, MODE(0) | RXACTIVE | PULLUP_EN);
+	write32(&regs->mmc0_dat2, MODE(0) | RXACTIVE | PULLUP_EN);
+	write32(&regs->mmc0_dat3, MODE(0) | RXACTIVE | PULLUP_EN);
+	write32(&regs->mmc0_clk, MODE(0) | RXACTIVE | PULLUP_EN);
+	write32(&regs->mmc0_cmd, MODE(0) | RXACTIVE | PULLUP_EN);
 	if (!sk_evm) {
 		// MMC0_WP
-		writel(MODE(4) | RXACTIVE, &regs->mcasp0_aclkr);
+		write32(&regs->mcasp0_aclkr, MODE(4) | RXACTIVE);
 	}
 	if (cd) {
 		// MMC0_CD
-		writel(MODE(5) | RXACTIVE | PULLUP_EN, &regs->spi0_cs1);
+		write32(&regs->spi0_cs1, MODE(5) | RXACTIVE | PULLUP_EN);
 	}
 }
 
 void am335x_pinmux_mmc1(void)
 {
 	// MMC1_DAT0
-	writel(MODE(1) | RXACTIVE | PULLUP_EN, &regs->gpmc_ad0);
+	write32(&regs->gpmc_ad0, MODE(1) | RXACTIVE | PULLUP_EN);
 	// MMC1_DAT1
-	writel(MODE(1) | RXACTIVE | PULLUP_EN, &regs->gpmc_ad1);
+	write32(&regs->gpmc_ad1, MODE(1) | RXACTIVE | PULLUP_EN);
 	// MMC1_DAT2
-	writel(MODE(1) | RXACTIVE | PULLUP_EN, &regs->gpmc_ad2);
+	write32(&regs->gpmc_ad2, MODE(1) | RXACTIVE | PULLUP_EN);
 	// MMC1_DAT3
-	writel(MODE(1) | RXACTIVE | PULLUP_EN, &regs->gpmc_ad3);
+	write32(&regs->gpmc_ad3, MODE(1) | RXACTIVE | PULLUP_EN);
 	// MMC1_CLK
-	writel(MODE(2) | RXACTIVE | PULLUP_EN, &regs->gpmc_csn1);
+	write32(&regs->gpmc_csn1, MODE(2) | RXACTIVE | PULLUP_EN);
 	// MMC1_CMD
-	writel(MODE(2) | RXACTIVE | PULLUP_EN, &regs->gpmc_csn2);
+	write32(&regs->gpmc_csn2, MODE(2) | RXACTIVE | PULLUP_EN);
 	// MMC1_WP
-	writel(MODE(7) | RXACTIVE | PULLUP_EN, &regs->gpmc_csn0);
+	write32(&regs->gpmc_csn0, MODE(7) | RXACTIVE | PULLUP_EN);
 	// MMC1_CD
-	writel(MODE(7) | RXACTIVE | PULLUP_EN, &regs->gpmc_advn_ale);
+	write32(&regs->gpmc_advn_ale, MODE(7) | RXACTIVE | PULLUP_EN);
 }
 
 void am335x_pinmux_i2c0(void)
 {
-	writel(MODE(0) | RXACTIVE | PULLUDEN | SLEWCTRL, &regs->i2c0_sda);
-	writel(MODE(0) | RXACTIVE | PULLUDEN | SLEWCTRL, &regs->i2c0_scl);
+	write32(&regs->i2c0_sda, MODE(0) | RXACTIVE | PULLUDEN | SLEWCTRL);
+	write32(&regs->i2c0_scl, MODE(0) | RXACTIVE | PULLUDEN | SLEWCTRL);
 }
 
 void am335x_pinmux_i2c1(void)
 {
 	// I2C_DATA
-	writel(MODE(2) | RXACTIVE | PULLUDEN | SLEWCTRL, &regs->spi0_d1);
+	write32(&regs->spi0_d1, MODE(2) | RXACTIVE | PULLUDEN | SLEWCTRL);
 	// I2C_SCLK
-	writel(MODE(2) | RXACTIVE | PULLUDEN | SLEWCTRL, &regs->spi0_cs0);
+	write32(&regs->spi0_cs0, MODE(2) | RXACTIVE | PULLUDEN | SLEWCTRL);
 }
 
 void am335x_pinmux_spi0(void)
 {
-	writel(MODE(0) | RXACTIVE | PULLUDEN, &regs->spi0_sclk);
-	writel(MODE(0) | RXACTIVE | PULLUDEN | PULLUP_EN, &regs->spi0_d0);
-	writel(MODE(0) | RXACTIVE | PULLUDEN, &regs->spi0_d1);
-	writel(MODE(0) | RXACTIVE | PULLUDEN | PULLUP_EN, &regs->spi0_cs0);
+	write32(&regs->spi0_sclk, MODE(0) | RXACTIVE | PULLUDEN);
+	write32(&regs->spi0_d0, MODE(0) | RXACTIVE | PULLUDEN | PULLUP_EN);
+	write32(&regs->spi0_d1, MODE(0) | RXACTIVE | PULLUDEN);
+	write32(&regs->spi0_cs0, MODE(0) | RXACTIVE | PULLUDEN | PULLUP_EN);
 }
 
 void am335x_pinmux_gpio0_7(void)
 {
-	writel(MODE(7) | PULLUDEN, &regs->ecap0_in_pwm0_out);
+	write32(&regs->ecap0_in_pwm0_out, MODE(7) | PULLUDEN);
 }
 
 void am335x_pinmux_rgmii1(void)
 {
-	writel(MODE(2), &regs->mii1_txen);
-	writel(MODE(2) | RXACTIVE, &regs->mii1_rxdv);
-	writel(MODE(2), &regs->mii1_txd0);
-	writel(MODE(2), &regs->mii1_txd1);
-	writel(MODE(2), &regs->mii1_txd2);
-	writel(MODE(2), &regs->mii1_txd3);
-	writel(MODE(2), &regs->mii1_txclk);
-	writel(MODE(2) | RXACTIVE, &regs->mii1_rxclk);
-	writel(MODE(2) | RXACTIVE, &regs->mii1_rxd0);
-	writel(MODE(2) | RXACTIVE, &regs->mii1_rxd1);
-	writel(MODE(2) | RXACTIVE, &regs->mii1_rxd2);
-	writel(MODE(2) | RXACTIVE, &regs->mii1_rxd3);
+	write32(&regs->mii1_txen, MODE(2));
+	write32(&regs->mii1_rxdv, MODE(2) | RXACTIVE);
+	write32(&regs->mii1_txd0, MODE(2));
+	write32(&regs->mii1_txd1, MODE(2));
+	write32(&regs->mii1_txd2, MODE(2));
+	write32(&regs->mii1_txd3, MODE(2));
+	write32(&regs->mii1_txclk, MODE(2));
+	write32(&regs->mii1_rxclk, MODE(2) | RXACTIVE);
+	write32(&regs->mii1_rxd0, MODE(2) | RXACTIVE);
+	write32(&regs->mii1_rxd1, MODE(2) | RXACTIVE);
+	write32(&regs->mii1_rxd2, MODE(2) | RXACTIVE);
+	write32(&regs->mii1_rxd3, MODE(2) | RXACTIVE);
 }
 
 void am335x_pinmux_mii1(void)
 {
-	writel(MODE(0) | RXACTIVE, &regs->mii1_rxerr);
-	writel(MODE(0), &regs->mii1_txen);
-	writel(MODE(0) | RXACTIVE, &regs->mii1_rxdv);
-	writel(MODE(0), &regs->mii1_txd0);
-	writel(MODE(0), &regs->mii1_txd1);
-	writel(MODE(0), &regs->mii1_txd2);
-	writel(MODE(0), &regs->mii1_txd3);
-	writel(MODE(0) | RXACTIVE, &regs->mii1_txclk);
-	writel(MODE(0) | RXACTIVE, &regs->mii1_rxclk);
-	writel(MODE(0) | RXACTIVE, &regs->mii1_rxd0);
-	writel(MODE(0) | RXACTIVE, &regs->mii1_rxd1);
-	writel(MODE(0) | RXACTIVE, &regs->mii1_rxd2);
-	writel(MODE(0) | RXACTIVE, &regs->mii1_rxd3);
-	writel(MODE(0) | RXACTIVE | PULLUP_EN, &regs->mdio_data);
-	writel(MODE(0) | PULLUP_EN, &regs->mdio_clk);
+	write32(&regs->mii1_rxerr, MODE(0) | RXACTIVE);
+	write32(&regs->mii1_txen, MODE(0));
+	write32(&regs->mii1_rxdv, MODE(0) | RXACTIVE);
+	write32(&regs->mii1_txd0, MODE(0));
+	write32(&regs->mii1_txd1, MODE(0));
+	write32(&regs->mii1_txd2, MODE(0));
+	write32(&regs->mii1_txd3, MODE(0));
+	write32(&regs->mii1_txclk, MODE(0) | RXACTIVE);
+	write32(&regs->mii1_rxclk, MODE(0) | RXACTIVE);
+	write32(&regs->mii1_rxd0, MODE(0) | RXACTIVE);
+	write32(&regs->mii1_rxd1, MODE(0) | RXACTIVE);
+	write32(&regs->mii1_rxd2, MODE(0) | RXACTIVE);
+	write32(&regs->mii1_rxd3, MODE(0) | RXACTIVE);
+	write32(&regs->mdio_data, MODE(0) | RXACTIVE | PULLUP_EN);
+	write32(&regs->mdio_clk, MODE(0) | PULLUP_EN);
 }
 
 void am335x_pinmux_nand(void)
 {
-	writel(MODE(0) | PULLUP_EN | RXACTIVE, &regs->gpmc_ad0);
-	writel(MODE(0) | PULLUP_EN | RXACTIVE, &regs->gpmc_ad1);
-	writel(MODE(0) | PULLUP_EN | RXACTIVE, &regs->gpmc_ad2);
-	writel(MODE(0) | PULLUP_EN | RXACTIVE, &regs->gpmc_ad3);
-	writel(MODE(0) | PULLUP_EN | RXACTIVE, &regs->gpmc_ad4);
-	writel(MODE(0) | PULLUP_EN | RXACTIVE, &regs->gpmc_ad5);
-	writel(MODE(0) | PULLUP_EN | RXACTIVE, &regs->gpmc_ad6);
-	writel(MODE(0) | PULLUP_EN | RXACTIVE, &regs->gpmc_ad7);
-	writel(MODE(0) | RXACTIVE | PULLUP_EN, &regs->gpmc_wait0);
-	writel(MODE(7) | PULLUP_EN | RXACTIVE, &regs->gpmc_wpn);
-	writel(MODE(0) | PULLUDEN, &regs->gpmc_csn0);
-	writel(MODE(0) | PULLUDEN, &regs->gpmc_advn_ale);
-	writel(MODE(0) | PULLUDEN, &regs->gpmc_oen_ren);
-	writel(MODE(0) | PULLUDEN, &regs->gpmc_wen);
-	writel(MODE(0) | PULLUDEN, &regs->gpmc_be0n_cle);
+	write32(&regs->gpmc_ad0, MODE(0) | PULLUP_EN | RXACTIVE);
+	write32(&regs->gpmc_ad1, MODE(0) | PULLUP_EN | RXACTIVE);
+	write32(&regs->gpmc_ad2, MODE(0) | PULLUP_EN | RXACTIVE);
+	write32(&regs->gpmc_ad3, MODE(0) | PULLUP_EN | RXACTIVE);
+	write32(&regs->gpmc_ad4, MODE(0) | PULLUP_EN | RXACTIVE);
+	write32(&regs->gpmc_ad5, MODE(0) | PULLUP_EN | RXACTIVE);
+	write32(&regs->gpmc_ad6, MODE(0) | PULLUP_EN | RXACTIVE);
+	write32(&regs->gpmc_ad7, MODE(0) | PULLUP_EN | RXACTIVE);
+	write32(&regs->gpmc_wait0, MODE(0) | RXACTIVE | PULLUP_EN);
+	write32(&regs->gpmc_wpn, MODE(7) | PULLUP_EN | RXACTIVE);
+	write32(&regs->gpmc_csn0, MODE(0) | PULLUDEN);
+	write32(&regs->gpmc_advn_ale, MODE(0) | PULLUDEN);
+	write32(&regs->gpmc_oen_ren, MODE(0) | PULLUDEN);
+	write32(&regs->gpmc_wen, MODE(0) | PULLUDEN);
+	write32(&regs->gpmc_be0n_cle, MODE(0) | PULLUDEN);
 }
diff --git a/src/cpu/ti/am335x/uart.c b/src/cpu/ti/am335x/uart.c
index ef8e08cfb8..b2b7196649 100644
--- a/src/cpu/ti/am335x/uart.c
+++ b/src/cpu/ti/am335x/uart.c
@@ -42,88 +42,88 @@ static void am335x_uart_init(struct am335x_uart *uart, uint16_t div)
 	uint16_t lcr_orig, efr_orig, mcr_orig;
 
 	/* reset the UART */
-	writew(uart->sysc | SYSC_SOFTRESET, &uart->sysc);
+	write16(&uart->sysc, uart->sysc | SYSC_SOFTRESET);
 	while (!(read16(&uart->syss) & SYSS_RESETDONE))
 		;
 
 	/* 1. switch to register config mode B */
 	lcr_orig = read16(&uart->lcr);
-	writew(0xbf, &uart->lcr);
+	write16(&uart->lcr, 0xbf);
 
 	/*
 	 * 2. Set EFR ENHANCED_EN bit. To access this bit, registers must
 	 * be in TCR_TLR submode, meaning EFR[4] = 1 and MCR[6] = 1.
 	 */
 	efr_orig = read16(&uart->efr);
-	writew(efr_orig | EFR_ENHANCED_EN, &uart->efr);
+	write16(&uart->efr, efr_orig | EFR_ENHANCED_EN);
 
 	/* 3. Switch to register config mode A */
-	writew(0x80, &uart->lcr);
+	write16(&uart->lcr, 0x80);
 
 	/* 4. Enable register submode TCR_TLR to access the UARTi.UART_TLR */
 	mcr_orig = read16(&uart->mcr);
-	writew(mcr_orig | MCR_TCR_TLR, &uart->mcr);
+	write16(&uart->mcr, mcr_orig | MCR_TCR_TLR);
 
 	/* 5. Enable the FIFO. For now we'll ignore FIFO triggers and DMA */
-	writew(FCR_FIFO_EN, &uart->fcr);
+	write16(&uart->fcr, FCR_FIFO_EN);
 
 	/* 6. Switch to configuration mode B */
-	writew(0xbf, &uart->lcr);
+	write16(&uart->lcr, 0xbf);
 	/* Skip steps 7 and 8 (setting up FIFO triggers for DMA) */
 
 	/* 9. Restore original EFR value */
-	writew(efr_orig, &uart->efr);
+	write16(&uart->efr, efr_orig);
 
 	/* 10. Switch to config mode A */
-	writew(0x80, &uart->lcr);
+	write16(&uart->lcr, 0x80);
 
 	/* 11. Restore original MCR value */
-	writew(mcr_orig, &uart->mcr);
+	write16(&uart->mcr, mcr_orig);
 
 	/* 12. Restore original LCR value */
-	writew(lcr_orig, &uart->lcr);
+	write16(&uart->lcr, lcr_orig);
 
 	/* Protocol, baud rate and interrupt settings */
 
 	/* 1. Disable UART access to DLL and DLH registers */
-	writew(read16(&uart->mdr1) | 0x7, &uart->mdr1);
+	write16(&uart->mdr1, read16(&uart->mdr1) | 0x7);
 
 	/* 2. Switch to config mode B */
-	writew(0xbf, &uart->lcr);
+	write16(&uart->lcr, 0xbf);
 
 	/* 3. Enable access to IER[7:4] */
-	writew(efr_orig | EFR_ENHANCED_EN, &uart->efr);
+	write16(&uart->efr, efr_orig | EFR_ENHANCED_EN);
 
 	/* 4. Switch to operational mode */
-	writew(0x0, &uart->lcr);
+	write16(&uart->lcr, 0x0);
 
 	/* 5. Clear IER */
-	writew(0x0, &uart->ier);
+	write16(&uart->ier, 0x0);
 
 	/* 6. Switch to config mode B */
-	writew(0xbf, &uart->lcr);
+	write16(&uart->lcr, 0xbf);
 
 	/* 7. Set dll and dlh to the desired values (table 19-25) */
-	writew((div >> 8), &uart->dlh);
-	writew((div & 0xff), &uart->dll);
+	write16(&uart->dlh, (div >> 8));
+	write16(&uart->dll, (div & 0xff));
 
 	/* 8. Switch to operational mode to access ier */
-	writew(0x0, &uart->lcr);
+	write16(&uart->lcr, 0x0);
 
 	/* 9. Clear ier to disable all interrupts */
-	writew(0x0, &uart->ier);
+	write16(&uart->ier, 0x0);
 
 	/* 10. Switch to config mode B */
-	writew(0xbf, &uart->lcr);
+	write16(&uart->lcr, 0xbf);
 
 	/* 11. Restore efr */
-	writew(efr_orig, &uart->efr);
+	write16(&uart->efr, efr_orig);
 
 	/* 12. Set protocol formatting 8n1 (8 bit data, no parity, 1 stop bit) */
-	writew(0x3, &uart->lcr);
+	write16(&uart->lcr, 0x3);
 
 	/* 13. Load the new UART mode */
-	writew(0x0, &uart->mdr1);
+	write16(&uart->mdr1, 0x0);
 }
 
 /*
@@ -145,7 +145,7 @@ static void am335x_uart_tx_byte(struct am335x_uart *uart, unsigned char data)
 {
 	while (!(read16(&uart->lsr) & LSR_TXFIFOE));
 
-	return writeb(data, &uart->thr);
+	return write8(&uart->thr, data);
 }
 
 unsigned int uart_platform_refclk(void)