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| author | Patrick Rudolph <siro@das-labor.org> | 2016-03-13 11:07:45 +0100 |
|---|---|---|
| committer | Martin Roth <martinroth@google.com> | 2016-04-10 18:15:40 +0200 |
| commit | 56abd4d878e226c1c4499fdc28901711e2f2a95c (patch) | |
| tree | 15918925a3401decc9a517e0b6793441a460aa79 /src/cpu/ti | |
| parent | b2f9a10c189a267e834167e224b5d4be4c1f3269 (diff) | |
nb/intel/sandybridge/raminit: always use mrccache
Always use MRC cache if possible.
Added a CRC16 array to make sure the DIMMs haven't been replaced.
In case one of the CRC's doesn't match, start normal RAM training.
Use new fallback in case of broken mrc cache.
Test system:
* Gigabyte GA-B75M-D3H
* Intel Pentium CPU G2130
Test result:
The system boots a lot faster using the MRC cache.
On swapping DIMMs the CRC16 doesn't match and normal ram training
is started.
Change-Id: Ib48fe8380446846df17d37b22968f7d4fd6b9b13
Signed-off-by: Patrick Rudolph <siro@das-labor.org>
Reviewed-on: https://review.coreboot.org/14172
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Tested-by: build bot (Jenkins)
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Diffstat (limited to 'src/cpu/ti')
0 files changed, 0 insertions, 0 deletions