exynos5: Refactor crazy old U-Boot base address macros away

All this samsung_get_base_address_of_device_with_a_really_long_name()
boilerplate makes my eyes bleed... I think there are so much cleaner
ways to do this. Unfortunately changing this ends up touching nearly
every Exynos5 file, but I hope you agree that it's worth it (and the
sooner we get it over with, the better... I can't bring myself to make
another device fit into that ugly scheme).

This also removes the redundant EXYNOS5 base address definitions from
the 5420 directory when there are EXYNOS5420 ones, to avoid complete
confusion. The new scheme tries to use EXYNOS5 for base addresses and
exynos5 for types that are common between the two processors, and
EXYNOS5420/exynos5420 for things that have changes (although I probably
didn't catch all differences).

Change-Id: I87e58434490ed55a9bbe743af1f9bf2520dec13f
Signed-off-by: Julius Werner <jwerner@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/167579
Reviewed-by: Stefan Reinauer <reinauer@google.com>
Reviewed-by: David Hendricks <dhendrix@chromium.org>
Reviewed-by: ron minnich <rminnich@chromium.org>
(cherry picked from commit 66c87693352c248eec029c1ce83fb295059e6b5b)
Signed-off-by: Isaac Christensen <isaac.christensen@se-eng.com>
Reviewed-on: http://review.coreboot.org/6632
Tested-by: build bot (Jenkins)
Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
Reviewed-by: Edward O'Callaghan <eocallaghan@alterapraxis.com>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>

50 files changed, 1034 insertions, 1381 deletions

diff --git a/src/cpu/samsung/exynos5250/alternate_cbfs.c b/src/cpu/samsung/exynos5250/alternate_cbfs.c
index 59843fb97b..10b33f0c2b 100644
--- a/src/cpu/samsung/exynos5250/alternate_cbfs.c
+++ b/src/cpu/samsung/exynos5250/alternate_cbfs.c
@@ -24,7 +24,6 @@
 #include <string.h>
 #include <console/console.h>
 #include "alternate_cbfs.h"
-#include "cpu.h"
 #include "power.h"
 #include "spi.h"
 
@@ -162,7 +161,7 @@ int init_default_cbfs_media(struct cbfs_media *media)
 	if (*iram_secondary_base == SECONDARY_BASE_BOOT_USB)
 		return initialize_exynos_usb_cbfs_media(media);
 
-	switch (samsung_get_base_power()->om_stat & OM_STAT_MASK) {
+	switch (exynos_power->om_stat & OM_STAT_MASK) {
 	case OM_STAT_SDMMC:
 		return initialize_exynos_sdmmc_cbfs_media(media);
 	case OM_STAT_SPI:
@@ -171,7 +170,7 @@ int init_default_cbfs_media(struct cbfs_media *media)
 			CONFIG_CBFS_CACHE_SIZE);
 	default:
 		printk(BIOS_EMERG, "Exynos OM_STAT value 0x%x not supported!\n",
-			samsung_get_base_power()->om_stat);
+			exynos_power->om_stat);
 		return 0;
 	}
 }
diff --git a/src/cpu/samsung/exynos5250/alternate_cbfs.h b/src/cpu/samsung/exynos5250/alternate_cbfs.h
index 8a8727964b..72a30acc84 100644
--- a/src/cpu/samsung/exynos5250/alternate_cbfs.h
+++ b/src/cpu/samsung/exynos5250/alternate_cbfs.h
@@ -21,14 +21,14 @@
 #define CPU_SAMSUNG_EXYNOS5250_ALTERNATE_CBFS_H
 
 /* These are pointers to function pointers. Double indirection! */
-void * * const irom_sdmmc_read_blocks_ptr = (void * *)0x02020030;
-void * * const irom_msh_read_from_fifo_emmc_ptr = (void * *)0x02020044;
-void * * const irom_msh_end_boot_op_emmc_ptr = (void * *)0x02020048;
-void * * const irom_spi_sf_read_ptr = (void * *)0x02020058;
-void * * const irom_load_image_from_usb_ptr = (void * *)0x02020070;
+static void * * const irom_sdmmc_read_blocks_ptr = (void * *)0x02020030;
+static void * * const irom_msh_read_from_fifo_emmc_ptr = (void * *)0x02020044;
+static void * * const irom_msh_end_boot_op_emmc_ptr = (void * *)0x02020048;
+static void * * const irom_spi_sf_read_ptr = (void * *)0x02020058;
+static void * * const irom_load_image_from_usb_ptr = (void * *)0x02020070;
 
 #define SECONDARY_BASE_BOOT_USB 0xfeed0002
-u32 * const iram_secondary_base = (u32 *)0x02020018;
+static u32 * const iram_secondary_base = (u32 *)0x02020018;
 
 /* Values pulled from U-Boot, I think the manual is wrong here (for SPI) */
 #define OM_STAT_SDMMC 0x4
@@ -38,13 +38,14 @@ u32 * const iram_secondary_base = (u32 *)0x02020018;
 
 #if defined(__BOOT_BLOCK__)
 	/* A small space in IRAM to hold the romstage-only image */
-	void * const alternate_cbfs_buffer = (void *)CONFIG_CBFS_CACHE_ADDRESS;
-	size_t const alternate_cbfs_size = CONFIG_CBFS_CACHE_SIZE;
+	static void * const alternate_cbfs_buffer =
+			(void *)CONFIG_CBFS_CACHE_ADDRESS;
+	static size_t const alternate_cbfs_size = CONFIG_CBFS_CACHE_SIZE;
 #else
 	/* Just put this anywhere in RAM that's far enough from anything else */
 	/* TODO: Find a better way to "reserve" this region? */
-	void * const alternate_cbfs_buffer = (void *)0x77400000;
-	size_t const alternate_cbfs_size = 0xc00000;
+	static void * const alternate_cbfs_buffer = (void *)0x77400000;
+	static size_t const alternate_cbfs_size = 0xc00000;
 #endif
 
 #endif
diff --git a/src/cpu/samsung/exynos5250/clk.h b/src/cpu/samsung/exynos5250/clk.h
index 565cf2b255..f09ac41643 100644
--- a/src/cpu/samsung/exynos5250/clk.h
+++ b/src/cpu/samsung/exynos5250/clk.h
@@ -23,6 +23,8 @@
 
 #include <stdint.h>
 
+#include "cpu.h"
+
 enum periph_id;
 
 #define APLL	0
@@ -67,8 +69,6 @@ unsigned long clock_get_periph_rate(enum periph_id peripheral);
 #include "pinmux.h"
 
 
-#define MCT_ADDRESS 0x101c0000
-
 #define MCT_HZ 24000000
 
 /*
@@ -462,7 +462,9 @@ struct exynos5_clock {
 	unsigned char	res109b[0xf5e4];
 };
 
-struct exynos5_mct_regs {
+static struct exynos5_clock * const exynos_clock = (void *)EXYNOS5_CLOCK_BASE;
+
+struct exynos5_mct {
 	uint32_t	mct_cfg;
 	uint8_t		reserved0[0xfc];
 	uint32_t	g_cnt_l;
@@ -520,6 +522,9 @@ struct exynos5_mct_regs {
 	uint32_t	l1_wstat;
 };
 
+static struct exynos5_mct * const exynos_mct =
+		(void *)EXYNOS5_MULTI_CORE_TIMER_BASE;
+
 #define EXYNOS5_EPLLCON0_LOCKED_SHIFT	29  /* EPLL Locked bit position*/
 #define EPLL_SRC_CLOCK			24000000  /*24 MHz Crystal Input */
 #define TIMEOUT_EPLL_LOCK		1000
diff --git a/src/cpu/samsung/exynos5250/clock.c b/src/cpu/samsung/exynos5250/clock.c
index a89ceb393a..f012c20ca0 100644
--- a/src/cpu/samsung/exynos5250/clock.c
+++ b/src/cpu/samsung/exynos5250/clock.c
@@ -17,14 +17,13 @@
  * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
  */
 
-#include <console/console.h>
-#include <stdlib.h>
 #include <assert.h>
+#include <stdlib.h>
 #include <arch/io.h>
-#include "timer.h"
+#include <console/console.h>
 #include "clk.h"
-#include "cpu.h"
 #include "periph.h"
+#include "timer.h"
 
 /* input clock of PLL: SMDK5250 has 24MHz input clock */
 #define CONFIG_SYS_CLK_FREQ            24000000
@@ -174,28 +173,26 @@ static struct st_epll_con_val epll_div[] = {
 /* exynos5: return pll clock frequency */
 unsigned long get_pll_clk(int pllreg)
 {
-	struct exynos5_clock *clk =
-		samsung_get_base_clock();
 	unsigned long r, m, p, s, k = 0, mask, fout;
 	unsigned int freq;
 
 	switch (pllreg) {
 	case APLL:
-		r = readl(&clk->apll_con0);
+		r = readl(&exynos_clock->apll_con0);
 		break;
 	case BPLL:
-		r = readl(&clk->bpll_con0);
+		r = readl(&exynos_clock->bpll_con0);
 		break;
 	case MPLL:
-		r = readl(&clk->mpll_con0);
+		r = readl(&exynos_clock->mpll_con0);
 		break;
 	case EPLL:
-		r = readl(&clk->epll_con0);
-		k = readl(&clk->epll_con1);
+		r = readl(&exynos_clock->epll_con0);
+		k = readl(&exynos_clock->epll_con1);
 		break;
 	case VPLL:
-		r = readl(&clk->vpll_con0);
-		k = readl(&clk->vpll_con1);
+		r = readl(&exynos_clock->vpll_con0);
+		k = readl(&exynos_clock->vpll_con1);
 		break;
 	default:
 		printk(BIOS_DEBUG, "Unsupported PLL (%d)\n", pllreg);
@@ -240,8 +237,6 @@ unsigned long get_pll_clk(int pllreg)
 
 unsigned long clock_get_periph_rate(enum periph_id peripheral)
 {
-	struct exynos5_clock *clk =
-		samsung_get_base_clock();
 	struct clk_bit_info *bit_info = &clk_bit_info[peripheral];
 	unsigned long sclk, sub_clk;
 	unsigned int src, div, sub_div;
@@ -251,41 +246,41 @@ unsigned long clock_get_periph_rate(enum periph_id peripheral)
 	case PERIPH_ID_UART1:
 	case PERIPH_ID_UART2:
 	case PERIPH_ID_UART3:
-		src = readl(&clk->src_peric0);
-		div = readl(&clk->div_peric0);
+		src = readl(&exynos_clock->src_peric0);
+		div = readl(&exynos_clock->div_peric0);
 		break;
 	case PERIPH_ID_PWM0:
 	case PERIPH_ID_PWM1:
 	case PERIPH_ID_PWM2:
 	case PERIPH_ID_PWM3:
 	case PERIPH_ID_PWM4:
-		src = readl(&clk->src_peric0);
-		div = readl(&clk->div_peric3);
+		src = readl(&exynos_clock->src_peric0);
+		div = readl(&exynos_clock->div_peric3);
 		break;
 	case PERIPH_ID_SPI0:
 	case PERIPH_ID_SPI1:
-		src = readl(&clk->src_peric1);
-		div = readl(&clk->div_peric1);
+		src = readl(&exynos_clock->src_peric1);
+		div = readl(&exynos_clock->div_peric1);
 		break;
 	case PERIPH_ID_SPI2:
-		src = readl(&clk->src_peric1);
-		div = readl(&clk->div_peric2);
+		src = readl(&exynos_clock->src_peric1);
+		div = readl(&exynos_clock->div_peric2);
 		break;
 	case PERIPH_ID_SPI3:
 	case PERIPH_ID_SPI4:
-		src = readl(&clk->sclk_src_isp);
-		div = readl(&clk->sclk_div_isp);
+		src = readl(&exynos_clock->sclk_src_isp);
+		div = readl(&exynos_clock->sclk_div_isp);
 		break;
 	case PERIPH_ID_SATA:
-		src = readl(&clk->src_fsys);
-		div = readl(&clk->div_fsys0);
+		src = readl(&exynos_clock->src_fsys);
+		div = readl(&exynos_clock->div_fsys0);
 		break;
 	case PERIPH_ID_SDMMC0:
 	case PERIPH_ID_SDMMC1:
 	case PERIPH_ID_SDMMC2:
 	case PERIPH_ID_SDMMC3:
-		src = readl(&clk->src_fsys);
-		div = readl(&clk->div_fsys1);
+		src = readl(&exynos_clock->src_fsys);
+		div = readl(&exynos_clock->div_fsys1);
 		break;
 	case PERIPH_ID_I2C0:
 	case PERIPH_ID_I2C1:
@@ -296,8 +291,10 @@ unsigned long clock_get_periph_rate(enum periph_id peripheral)
 	case PERIPH_ID_I2C6:
 	case PERIPH_ID_I2C7:
 		sclk = get_pll_clk(MPLL);
-		sub_div = ((readl(&clk->div_top1) >> bit_info->div_bit) & 0x7) + 1;
-		div = ((readl(&clk->div_top0) >> bit_info->prediv_bit) & 0x7) + 1;
+		sub_div = ((readl(&exynos_clock->div_top1)
+			    >> bit_info->div_bit) & 0x7) + 1;
+		div = ((readl(&exynos_clock->div_top0)
+		        >> bit_info->prediv_bit) & 0x7) + 1;
 		return (sclk / sub_div) / div;
 	default:
 		printk(BIOS_DEBUG, "%s: invalid peripheral %d", __func__, peripheral);
@@ -335,14 +332,12 @@ unsigned long clock_get_periph_rate(enum periph_id peripheral)
 /* exynos5: return ARM clock frequency */
 unsigned long get_arm_clk(void)
 {
-	struct exynos5_clock *clk =
-		samsung_get_base_clock();
 	unsigned long div;
 	unsigned long armclk;
 	unsigned int arm_ratio;
 	unsigned int arm2_ratio;
 
-	div = readl(&clk->div_cpu0);
+	div = readl(&exynos_clock->div_cpu0);
 
 	/* ARM_RATIO: [2:0], ARM2_RATIO: [30:28] */
 	arm_ratio = (div >> 0) & 0x7;
@@ -372,8 +367,6 @@ struct arm_clk_ratios *get_arm_clk_ratios(void)
 /* exynos5: set the mmc clock */
 void set_mmc_clk(int dev_index, unsigned int div)
 {
-	struct exynos5_clock *clk =
-		samsung_get_base_clock();
 	unsigned int *addr;
 	unsigned int val;
 
@@ -384,9 +377,9 @@ void set_mmc_clk(int dev_index, unsigned int div)
 	 * MMC2_PRE_RATIO [15:8], MMC3_PRE_RATIO [31:24]
 	 */
 	if (dev_index < 2) {
-		addr = &clk->div_fsys1;
+		addr = &exynos_clock->div_fsys1;
 	} else {
-		addr = &clk->div_fsys2;
+		addr = &exynos_clock->div_fsys2;
 		dev_index -= 2;
 	}
 
@@ -398,8 +391,6 @@ void set_mmc_clk(int dev_index, unsigned int div)
 
 void clock_ll_set_pre_ratio(enum periph_id periph_id, unsigned divisor)
 {
-	struct exynos5_clock *clk =
-		samsung_get_base_clock();
 	unsigned shift;
 	unsigned mask = 0xff;
 	u32 *reg;
@@ -414,23 +405,23 @@ void clock_ll_set_pre_ratio(enum periph_id periph_id, unsigned divisor)
 	 */
 	switch (periph_id) {
 	case PERIPH_ID_SPI0:
-		reg = &clk->div_peric1;
+		reg = &exynos_clock->div_peric1;
 		shift = 8;
 		break;
 	case PERIPH_ID_SPI1:
-		reg = &clk->div_peric1;
+		reg = &exynos_clock->div_peric1;
 		shift = 24;
 		break;
 	case PERIPH_ID_SPI2:
-		reg = &clk->div_peric2;
+		reg = &exynos_clock->div_peric2;
 		shift = 8;
 		break;
 	case PERIPH_ID_SPI3:
-		reg = &clk->sclk_div_isp;
+		reg = &exynos_clock->sclk_div_isp;
 		shift = 4;
 		break;
 	case PERIPH_ID_SPI4:
-		reg = &clk->sclk_div_isp;
+		reg = &exynos_clock->sclk_div_isp;
 		shift = 16;
 		break;
 	default:
@@ -443,31 +434,29 @@ void clock_ll_set_pre_ratio(enum periph_id periph_id, unsigned divisor)
 
 void clock_ll_set_ratio(enum periph_id periph_id, unsigned divisor)
 {
-	struct exynos5_clock *clk =
-		samsung_get_base_clock();
 	unsigned shift;
 	unsigned mask = 0xff;
 	u32 *reg;
 
 	switch (periph_id) {
 	case PERIPH_ID_SPI0:
-		reg = &clk->div_peric1;
+		reg = &exynos_clock->div_peric1;
 		shift = 0;
 		break;
 	case PERIPH_ID_SPI1:
-		reg = &clk->div_peric1;
+		reg = &exynos_clock->div_peric1;
 		shift = 16;
 		break;
 	case PERIPH_ID_SPI2:
-		reg = &clk->div_peric2;
+		reg = &exynos_clock->div_peric2;
 		shift = 0;
 		break;
 	case PERIPH_ID_SPI3:
-		reg = &clk->sclk_div_isp;
+		reg = &exynos_clock->sclk_div_isp;
 		shift = 0;
 		break;
 	case PERIPH_ID_SPI4:
-		reg = &clk->sclk_div_isp;
+		reg = &exynos_clock->sclk_div_isp;
 		shift = 12;
 		break;
 	default:
@@ -568,8 +557,6 @@ int clock_set_rate(enum periph_id periph_id, unsigned int rate)
 
 int clock_set_mshci(enum periph_id peripheral)
 {
-	struct exynos5_clock *clk =
-		samsung_get_base_clock();
 	u32 *addr;
 	unsigned int clock;
 	unsigned int tmp;
@@ -586,10 +573,10 @@ int clock_set_mshci(enum periph_id peripheral)
 	 */
 	switch (peripheral) {
 	case PERIPH_ID_SDMMC0:
-		addr = &clk->div_fsys1;
+		addr = &exynos_clock->div_fsys1;
 		break;
 	case PERIPH_ID_SDMMC2:
-		addr = &clk->div_fsys2;
+		addr = &exynos_clock->div_fsys2;
 		break;
 	default:
 		printk(BIOS_DEBUG, "invalid peripheral\n");
@@ -611,9 +598,8 @@ int clock_epll_set_rate(unsigned long rate)
 	unsigned int i;
 	unsigned int lockcnt;
 	struct mono_time current, end;
-	struct exynos5_clock *clk = samsung_get_base_clock();
 
-	epll_con = readl(&clk->epll_con0);
+	epll_con = readl(&exynos_clock->epll_con0);
 	epll_con &= ~((EPLL_CON0_LOCK_DET_EN_MASK <<
 			EPLL_CON0_LOCK_DET_EN_SHIFT) |
 		EPLL_CON0_MDIV_MASK << EPLL_CON0_MDIV_SHIFT |
@@ -641,15 +627,15 @@ int clock_epll_set_rate(unsigned long rate)
 	 */
 	lockcnt = 3000 * epll_div[i].p_div;
 
-	writel(lockcnt, &clk->epll_lock);
-	writel(epll_con, &clk->epll_con0);
-	writel(epll_con_k, &clk->epll_con1);
+	writel(lockcnt, &exynos_clock->epll_lock);
+	writel(epll_con, &exynos_clock->epll_con0);
+	writel(epll_con_k, &exynos_clock->epll_con1);
 
 	timer_monotonic_get(&current);
 	end = current;
 	mono_time_add_msecs(&end, TIMEOUT_EPLL_LOCK);
 
-	 while (!(readl(&clk->epll_con0) &
+	 while (!(readl(&exynos_clock->epll_con0) &
 			(0x1 << EXYNOS5_EPLLCON0_LOCKED_SHIFT))) {
 		if (mono_time_after(&current, &end)) {
 			printk(BIOS_DEBUG,
@@ -665,17 +651,12 @@ int clock_epll_set_rate(unsigned long rate)
 
 void clock_select_i2s_clk_source(void)
 {
-	struct exynos5_clock *clk =
-		samsung_get_base_clock();
-
-	clrsetbits_le32(&clk->src_peric1, AUDIO1_SEL_MASK,
+	clrsetbits_le32(&exynos_clock->src_peric1, AUDIO1_SEL_MASK,
 			(CLK_SRC_SCLK_EPLL));
 }
 
 int clock_set_i2s_clk_prescaler(unsigned int src_frq, unsigned int dst_frq)
 {
-	struct exynos5_clock *clk =
-		samsung_get_base_clock();
 	unsigned int div ;
 
 	if ((dst_frq == 0) || (src_frq == 0)) {
@@ -690,7 +671,7 @@ int clock_set_i2s_clk_prescaler(unsigned int src_frq, unsigned int dst_frq)
 		printk(BIOS_DEBUG, "src frq = %d des frq = %d ", src_frq, dst_frq);
 		return -1;
 	}
-	clrsetbits_le32(&clk->div_peric4, AUDIO_1_RATIO_MASK,
+	clrsetbits_le32(&exynos_clock->div_peric4, AUDIO_1_RATIO_MASK,
 				(div & AUDIO_1_RATIO_MASK));
 	return 0;
 }
diff --git a/src/cpu/samsung/exynos5250/clock_init.c b/src/cpu/samsung/exynos5250/clock_init.c
index cc260dbd93..c8cf3babfb 100644
--- a/src/cpu/samsung/exynos5250/clock_init.c
+++ b/src/cpu/samsung/exynos5250/clock_init.c
@@ -19,69 +19,65 @@
 
 /* Clock setup for SMDK5250 board based on EXYNOS5 */
 
-#include <console/console.h>
 #include <delay.h>
+#include <console/console.h>
 #include "clk.h"
-#include "cpu.h"
 #include "dp.h"
 #include "setup.h"
 
 void system_clock_init(struct mem_timings *mem,
 		struct arm_clk_ratios *arm_clk_ratio)
 {
-	struct exynos5_clock *clk = (struct exynos5_clock *)EXYNOS5_CLOCK_BASE;
-	struct exynos5_mct_regs *mct_regs =
-		(struct exynos5_mct_regs *)EXYNOS5_MULTI_CORE_TIMER_BASE;
 	u32 val, tmp;
 
 	/* Turn on the MCT as early as possible. */
-	mct_regs->g_tcon |= (1 << 8);
+	exynos_mct->g_tcon |= (1 << 8);
 
-	clrbits_le32(&clk->src_cpu, MUX_APLL_SEL_MASK);
+	clrbits_le32(&exynos_clock->src_cpu, MUX_APLL_SEL_MASK);
 	do {
-		val = readl(&clk->mux_stat_cpu);
+		val = readl(&exynos_clock->mux_stat_cpu);
 	} while ((val | MUX_APLL_SEL_MASK) != val);
 
-	clrbits_le32(&clk->src_core1, MUX_MPLL_SEL_MASK);
+	clrbits_le32(&exynos_clock->src_core1, MUX_MPLL_SEL_MASK);
 	do {
-		val = readl(&clk->mux_stat_core1);
+		val = readl(&exynos_clock->mux_stat_core1);
 	} while ((val | MUX_MPLL_SEL_MASK) != val);
 
-	clrbits_le32(&clk->src_top2, MUX_CPLL_SEL_MASK);
-	clrbits_le32(&clk->src_top2, MUX_EPLL_SEL_MASK);
-	clrbits_le32(&clk->src_top2, MUX_VPLL_SEL_MASK);
-	clrbits_le32(&clk->src_top2, MUX_GPLL_SEL_MASK);
+	clrbits_le32(&exynos_clock->src_top2, MUX_CPLL_SEL_MASK);
+	clrbits_le32(&exynos_clock->src_top2, MUX_EPLL_SEL_MASK);
+	clrbits_le32(&exynos_clock->src_top2, MUX_VPLL_SEL_MASK);
+	clrbits_le32(&exynos_clock->src_top2, MUX_GPLL_SEL_MASK);
 	tmp = MUX_CPLL_SEL_MASK | MUX_EPLL_SEL_MASK | MUX_VPLL_SEL_MASK
 		| MUX_GPLL_SEL_MASK;
 	do {
-		val = readl(&clk->mux_stat_top2);
+		val = readl(&exynos_clock->mux_stat_top2);
 	} while ((val | tmp) != val);
 
-	clrbits_le32(&clk->src_cdrex, MUX_BPLL_SEL_MASK);
+	clrbits_le32(&exynos_clock->src_cdrex, MUX_BPLL_SEL_MASK);
 	do {
-		val = readl(&clk->mux_stat_cdrex);
+		val = readl(&exynos_clock->mux_stat_cdrex);
 	} while ((val | MUX_BPLL_SEL_MASK) != val);
 
 	/* PLL locktime */
-	writel(APLL_LOCK_VAL, &clk->apll_lock);
+	writel(APLL_LOCK_VAL, &exynos_clock->apll_lock);
 
-	writel(MPLL_LOCK_VAL, &clk->mpll_lock);
+	writel(MPLL_LOCK_VAL, &exynos_clock->mpll_lock);
 
-	writel(BPLL_LOCK_VAL, &clk->bpll_lock);
+	writel(BPLL_LOCK_VAL, &exynos_clock->bpll_lock);
 
-	writel(CPLL_LOCK_VAL, &clk->cpll_lock);
+	writel(CPLL_LOCK_VAL, &exynos_clock->cpll_lock);
 
-	writel(GPLL_LOCK_VAL, &clk->gpll_lock);
+	writel(GPLL_LOCK_VAL, &exynos_clock->gpll_lock);
 
-	writel(EPLL_LOCK_VAL, &clk->epll_lock);
+	writel(EPLL_LOCK_VAL, &exynos_clock->epll_lock);
 
-	writel(VPLL_LOCK_VAL, &clk->vpll_lock);
+	writel(VPLL_LOCK_VAL, &exynos_clock->vpll_lock);
 
-	writel(CLK_REG_DISABLE, &clk->pll_div2_sel);
+	writel(CLK_REG_DISABLE, &exynos_clock->pll_div2_sel);
 
-	writel(MUX_HPM_SEL_MASK, &clk->src_cpu);
+	writel(MUX_HPM_SEL_MASK, &exynos_clock->src_cpu);
 	do {
-		val = readl(&clk->mux_stat_cpu);
+		val = readl(&exynos_clock->mux_stat_cpu);
 	} while ((val | HPM_SEL_SCLK_MPLL) != val);
 
 	val = arm_clk_ratio->arm2_ratio << 28
@@ -92,323 +88,321 @@ void system_clock_init(struct mem_timings *mem,
 		| arm_clk_ratio->acp_ratio << 8
 		| arm_clk_ratio->cpud_ratio << 4
 		| arm_clk_ratio->arm_ratio;
-	writel(val, &clk->div_cpu0);
+	writel(val, &exynos_clock->div_cpu0);
 	do {
-		val = readl(&clk->div_stat_cpu0);
+		val = readl(&exynos_clock->div_stat_cpu0);
 	} while (0 != val);
 
-	writel(CLK_DIV_CPU1_VAL, &clk->div_cpu1);
+	writel(CLK_DIV_CPU1_VAL, &exynos_clock->div_cpu1);
 	do {
-		val = readl(&clk->div_stat_cpu1);
+		val = readl(&exynos_clock->div_stat_cpu1);
 	} while (0 != val);
 
 	/* switch A15 clock source to OSC clock before changing APLL */
-	clrbits_le32(&clk->src_cpu, APLL_FOUT);
+	clrbits_le32(&exynos_clock->src_cpu, APLL_FOUT);
 
 	/* Set APLL */
-	writel(APLL_CON1_VAL, &clk->apll_con1);
+	writel(APLL_CON1_VAL, &exynos_clock->apll_con1);
 	val = set_pll(arm_clk_ratio->apll_mdiv, arm_clk_ratio->apll_pdiv,
 			arm_clk_ratio->apll_sdiv);
-	writel(val, &clk->apll_con0);
-	while ((readl(&clk->apll_con0) & APLL_CON0_LOCKED) == 0)
+	writel(val, &exynos_clock->apll_con0);
+	while ((readl(&exynos_clock->apll_con0) & APLL_CON0_LOCKED) == 0)
 		;
 
 	/* now it is safe to switch to APLL */
-	setbits_le32(&clk->src_cpu, APLL_FOUT);
+	setbits_le32(&exynos_clock->src_cpu, APLL_FOUT);
 
 	/* Set MPLL */
-	writel(MPLL_CON1_VAL, &clk->mpll_con1);
+	writel(MPLL_CON1_VAL, &exynos_clock->mpll_con1);
 	val = set_pll(mem->mpll_mdiv, mem->mpll_pdiv, mem->mpll_sdiv);
-	writel(val, &clk->mpll_con0);
-	while ((readl(&clk->mpll_con0) & MPLL_CON0_LOCKED) == 0)
+	writel(val, &exynos_clock->mpll_con0);
+	while ((readl(&exynos_clock->mpll_con0) & MPLL_CON0_LOCKED) == 0)
 		;
 
 	/*
 	 * Configure MUX_MPLL_FOUT to choose the direct clock source
 	 * path and avoid the fixed DIV/2 block to save power
 	 */
-	setbits_le32(&clk->pll_div2_sel, MUX_MPLL_FOUT_SEL);
+	setbits_le32(&exynos_clock->pll_div2_sel, MUX_MPLL_FOUT_SEL);
 
 	/* Set BPLL */
 	if (mem->use_bpll) {
-		writel(BPLL_CON1_VAL, &clk->bpll_con1);
+		writel(BPLL_CON1_VAL, &exynos_clock->bpll_con1);
 		val = set_pll(mem->bpll_mdiv, mem->bpll_pdiv, mem->bpll_sdiv);
-		writel(val, &clk->bpll_con0);
-		while ((readl(&clk->bpll_con0) & BPLL_CON0_LOCKED) == 0)
+		writel(val, &exynos_clock->bpll_con0);
+		while ((readl(&exynos_clock->bpll_con0) & BPLL_CON0_LOCKED) == 0)
 			;
 
-		setbits_le32(&clk->pll_div2_sel, MUX_BPLL_FOUT_SEL);
+		setbits_le32(&exynos_clock->pll_div2_sel, MUX_BPLL_FOUT_SEL);
 	}
 
 	/* Set CPLL */
-	writel(CPLL_CON1_VAL, &clk->cpll_con1);
+	writel(CPLL_CON1_VAL, &exynos_clock->cpll_con1);
 	val = set_pll(mem->cpll_mdiv, mem->cpll_pdiv, mem->cpll_sdiv);
-	writel(val, &clk->cpll_con0);
-	while ((readl(&clk->cpll_con0) & CPLL_CON0_LOCKED) == 0)
+	writel(val, &exynos_clock->cpll_con0);
+	while ((readl(&exynos_clock->cpll_con0) & CPLL_CON0_LOCKED) == 0)
 		;
 
 	/* Set GPLL */
-	writel(GPLL_CON1_VAL, &clk->gpll_con1);
+	writel(GPLL_CON1_VAL, &exynos_clock->gpll_con1);
 	val = set_pll(mem->gpll_mdiv, mem->gpll_pdiv, mem->gpll_sdiv);
-	writel(val, &clk->gpll_con0);
-	while ((readl(&clk->gpll_con0) & GPLL_CON0_LOCKED) == 0)
+	writel(val, &exynos_clock->gpll_con0);
+	while ((readl(&exynos_clock->gpll_con0) & GPLL_CON0_LOCKED) == 0)
 		;
 
 	/* Set EPLL */
-	writel(EPLL_CON2_VAL, &clk->epll_con2);
-	writel(EPLL_CON1_VAL, &clk->epll_con1);
+	writel(EPLL_CON2_VAL, &exynos_clock->epll_con2);
+	writel(EPLL_CON1_VAL, &exynos_clock->epll_con1);
 	val = set_pll(mem->epll_mdiv, mem->epll_pdiv, mem->epll_sdiv);
-	writel(val, &clk->epll_con0);
-	while ((readl(&clk->epll_con0) & EPLL_CON0_LOCKED) == 0)
+	writel(val, &exynos_clock->epll_con0);
+	while ((readl(&exynos_clock->epll_con0) & EPLL_CON0_LOCKED) == 0)
 		;
 
 	/* Set VPLL */
-	writel(VPLL_CON2_VAL, &clk->vpll_con2);
-	writel(VPLL_CON1_VAL, &clk->vpll_con1);
+	writel(VPLL_CON2_VAL, &exynos_clock->vpll_con2);
+	writel(VPLL_CON1_VAL, &exynos_clock->vpll_con1);
 	val = set_pll(mem->vpll_mdiv, mem->vpll_pdiv, mem->vpll_sdiv);
-	writel(val, &clk->vpll_con0);
-	while ((readl(&clk->vpll_con0) & VPLL_CON0_LOCKED) == 0)
+	writel(val, &exynos_clock->vpll_con0);
+	while ((readl(&exynos_clock->vpll_con0) & VPLL_CON0_LOCKED) == 0)
 		;
 
-	writel(CLK_SRC_CORE0_VAL, &clk->src_core0);
-	writel(CLK_DIV_CORE0_VAL, &clk->div_core0);
-	while (readl(&clk->div_stat_core0) != 0)
+	writel(CLK_SRC_CORE0_VAL, &exynos_clock->src_core0);
+	writel(CLK_DIV_CORE0_VAL, &exynos_clock->div_core0);
+	while (readl(&exynos_clock->div_stat_core0) != 0)
 		;
 
-	writel(CLK_DIV_CORE1_VAL, &clk->div_core1);
-	while (readl(&clk->div_stat_core1) != 0)
+	writel(CLK_DIV_CORE1_VAL, &exynos_clock->div_core1);
+	while (readl(&exynos_clock->div_stat_core1) != 0)
 		;
 
-	writel(CLK_DIV_SYSRGT_VAL, &clk->div_sysrgt);
-	while (readl(&clk->div_stat_sysrgt) != 0)
+	writel(CLK_DIV_SYSRGT_VAL, &exynos_clock->div_sysrgt);
+	while (readl(&exynos_clock->div_stat_sysrgt) != 0)
 		;
 
-	writel(CLK_DIV_ACP_VAL, &clk->div_acp);
-	while (readl(&clk->div_stat_acp) != 0)
+	writel(CLK_DIV_ACP_VAL, &exynos_clock->div_acp);
+	while (readl(&exynos_clock->div_stat_acp) != 0)
 		;
 
-	writel(CLK_DIV_SYSLFT_VAL, &clk->div_syslft);
-	while (readl(&clk->div_stat_syslft) != 0)
+	writel(CLK_DIV_SYSLFT_VAL, &exynos_clock->div_syslft);
+	while (readl(&exynos_clock->div_stat_syslft) != 0)
 		;
 
-	writel(CLK_SRC_TOP0_VAL, &clk->src_top0);
-	writel(CLK_SRC_TOP1_VAL, &clk->src_top1);
-	writel(TOP2_VAL, &clk->src_top2);
-	writel(CLK_SRC_TOP3_VAL, &clk->src_top3);
+	writel(CLK_SRC_TOP0_VAL, &exynos_clock->src_top0);
+	writel(CLK_SRC_TOP1_VAL, &exynos_clock->src_top1);
+	writel(TOP2_VAL, &exynos_clock->src_top2);
+	writel(CLK_SRC_TOP3_VAL, &exynos_clock->src_top3);
 
-	writel(CLK_DIV_TOP0_VAL, &clk->div_top0);
-	while (readl(&clk->div_stat_top0))
+	writel(CLK_DIV_TOP0_VAL, &exynos_clock->div_top0);
+	while (readl(&exynos_clock->div_stat_top0))
 		;
 
-	writel(CLK_DIV_TOP1_VAL, &clk->div_top1);
-	while (readl(&clk->div_stat_top1))
+	writel(CLK_DIV_TOP1_VAL, &exynos_clock->div_top1);
+	while (readl(&exynos_clock->div_stat_top1))
 		;
 
-	writel(CLK_SRC_LEX_VAL, &clk->src_lex);
+	writel(CLK_SRC_LEX_VAL, &exynos_clock->src_lex);
 	while (1) {
-		val = readl(&clk->mux_stat_lex);
+		val = readl(&exynos_clock->mux_stat_lex);
 		if (val == (val | 1))
 			break;
 	}
 
-	writel(CLK_DIV_LEX_VAL, &clk->div_lex);
-	while (readl(&clk->div_stat_lex))
+	writel(CLK_DIV_LEX_VAL, &exynos_clock->div_lex);
+	while (readl(&exynos_clock->div_stat_lex))
 		;
 
-	writel(CLK_DIV_R0X_VAL, &clk->div_r0x);
-	while (readl(&clk->div_stat_r0x))
+	writel(CLK_DIV_R0X_VAL, &exynos_clock->div_r0x);
+	while (readl(&exynos_clock->div_stat_r0x))
 		;
 
-	writel(CLK_DIV_R0X_VAL, &clk->div_r0x);
-	while (readl(&clk->div_stat_r0x))
+	writel(CLK_DIV_R0X_VAL, &exynos_clock->div_r0x);
+	while (readl(&exynos_clock->div_stat_r0x))
 		;
 
-	writel(CLK_DIV_R1X_VAL, &clk->div_r1x);
-	while (readl(&clk->div_stat_r1x))
+	writel(CLK_DIV_R1X_VAL, &exynos_clock->div_r1x);
+	while (readl(&exynos_clock->div_stat_r1x))
 		;
 
 	if (mem->use_bpll) {
 		writel(MUX_BPLL_SEL_MASK | MUX_MCLK_CDREX_SEL |
-			MUX_MCLK_DPHY_SEL, &clk->src_cdrex);
+			MUX_MCLK_DPHY_SEL, &exynos_clock->src_cdrex);
 	} else {
-		writel(CLK_REG_DISABLE, &clk->src_cdrex);
+		writel(CLK_REG_DISABLE, &exynos_clock->src_cdrex);
 	}
 
-	writel(CLK_DIV_CDREX_VAL, &clk->div_cdrex);
-	while (readl(&clk->div_stat_cdrex))
+	writel(CLK_DIV_CDREX_VAL, &exynos_clock->div_cdrex);
+	while (readl(&exynos_clock->div_stat_cdrex))
 		;
 
-	val = readl(&clk->src_cpu);
+	val = readl(&exynos_clock->src_cpu);
 	val |= CLK_SRC_CPU_VAL;
-	writel(val, &clk->src_cpu);
+	writel(val, &exynos_clock->src_cpu);
 
-	val = readl(&clk->src_top2);
+	val = readl(&exynos_clock->src_top2);
 	val |= CLK_SRC_TOP2_VAL;
-	writel(val, &clk->src_top2);
+	writel(val, &exynos_clock->src_top2);
 
-	val = readl(&clk->src_core1);
+	val = readl(&exynos_clock->src_core1);
 	val |= CLK_SRC_CORE1_VAL;
-	writel(val, &clk->src_core1);
+	writel(val, &exynos_clock->src_core1);
 
-	writel(CLK_SRC_FSYS0_VAL, &clk->src_fsys);
-	writel(CLK_DIV_FSYS0_VAL, &clk->div_fsys0);
-	while (readl(&clk->div_stat_fsys0))
+	writel(CLK_SRC_FSYS0_VAL, &exynos_clock->src_fsys);
+	writel(CLK_DIV_FSYS0_VAL, &exynos_clock->div_fsys0);
+	while (readl(&exynos_clock->div_stat_fsys0))
 		;
 
-	writel(CLK_REG_DISABLE, &clk->clkout_cmu_cpu);
-	writel(CLK_REG_DISABLE, &clk->clkout_cmu_core);
-	writel(CLK_REG_DISABLE, &clk->clkout_cmu_acp);
-	writel(CLK_REG_DISABLE, &clk->clkout_cmu_top);
-	writel(CLK_REG_DISABLE, &clk->clkout_cmu_lex);
-	writel(CLK_REG_DISABLE, &clk->clkout_cmu_r0x);
-	writel(CLK_REG_DISABLE, &clk->clkout_cmu_r1x);
-	writel(CLK_REG_DISABLE, &clk->clkout_cmu_cdrex);
-
-	writel(CLK_SRC_PERIC0_VAL, &clk->src_peric0);
-	writel(CLK_DIV_PERIC0_VAL, &clk->div_peric0);
-
-	writel(CLK_SRC_PERIC1_VAL, &clk->src_peric1);
-	writel(CLK_DIV_PERIC1_VAL, &clk->div_peric1);
-	writel(CLK_DIV_PERIC2_VAL, &clk->div_peric2);
-	writel(SCLK_SRC_ISP_VAL, &clk->sclk_src_isp);
-	writel(SCLK_DIV_ISP_VAL, &clk->sclk_div_isp);
-	writel(CLK_DIV_ISP0_VAL, &clk->div_isp0);
-	writel(CLK_DIV_ISP1_VAL, &clk->div_isp1);
-	writel(CLK_DIV_ISP2_VAL, &clk->div_isp2);
+	writel(CLK_REG_DISABLE, &exynos_clock->clkout_cmu_cpu);
+	writel(CLK_REG_DISABLE, &exynos_clock->clkout_cmu_core);
+	writel(CLK_REG_DISABLE, &exynos_clock->clkout_cmu_acp);
+	writel(CLK_REG_DISABLE, &exynos_clock->clkout_cmu_top);
+	writel(CLK_REG_DISABLE, &exynos_clock->clkout_cmu_lex);
+	writel(CLK_REG_DISABLE, &exynos_clock->clkout_cmu_r0x);
+	writel(CLK_REG_DISABLE, &exynos_clock->clkout_cmu_r1x);
+	writel(CLK_REG_DISABLE, &exynos_clock->clkout_cmu_cdrex);
+
+	writel(CLK_SRC_PERIC0_VAL, &exynos_clock->src_peric0);
+	writel(CLK_DIV_PERIC0_VAL, &exynos_clock->div_peric0);
+
+	writel(CLK_SRC_PERIC1_VAL, &exynos_clock->src_peric1);
+	writel(CLK_DIV_PERIC1_VAL, &exynos_clock->div_peric1);
+	writel(CLK_DIV_PERIC2_VAL, &exynos_clock->div_peric2);
+	writel(SCLK_SRC_ISP_VAL, &exynos_clock->sclk_src_isp);
+	writel(SCLK_DIV_ISP_VAL, &exynos_clock->sclk_div_isp);
+	writel(CLK_DIV_ISP0_VAL, &exynos_clock->div_isp0);
+	writel(CLK_DIV_ISP1_VAL, &exynos_clock->div_isp1);
+	writel(CLK_DIV_ISP2_VAL, &exynos_clock->div_isp2);
 
 	/* FIMD1 SRC CLK SELECTION */
-	writel(CLK_SRC_DISP1_0_VAL, &clk->src_disp1_0);
+	writel(CLK_SRC_DISP1_0_VAL, &exynos_clock->src_disp1_0);
 
 	val = MMC2_PRE_RATIO_VAL << MMC2_PRE_RATIO_OFFSET
 		| MMC2_RATIO_VAL << MMC2_RATIO_OFFSET
 		| MMC3_PRE_RATIO_VAL << MMC3_PRE_RATIO_OFFSET
 		| MMC3_RATIO_VAL << MMC3_RATIO_OFFSET;
-	writel(val, &clk->div_fsys2);
+	writel(val, &exynos_clock->div_fsys2);
 }
 
 void clock_gate(void)
 {
-	struct exynos5_clock *clk = (struct exynos5_clock *)EXYNOS5_CLOCK_BASE;
-
 	/* CLK_GATE_IP_SYSRGT */
-	clrbits_le32(&clk->gate_ip_sysrgt, CLK_C2C_MASK);
+	clrbits_le32(&exynos_clock->gate_ip_sysrgt, CLK_C2C_MASK);
 
 	/* CLK_GATE_IP_ACP */
-	clrbits_le32(&clk->gate_ip_acp, CLK_SMMUG2D_MASK |
-					CLK_SMMUSSS_MASK |
-					CLK_SMMUMDMA_MASK |
-					CLK_ID_REMAPPER_MASK |
-					CLK_G2D_MASK |
-					CLK_SSS_MASK |
-					CLK_MDMA_MASK |
-					CLK_SECJTAG_MASK);
+	clrbits_le32(&exynos_clock->gate_ip_acp, CLK_SMMUG2D_MASK |
+						 CLK_SMMUSSS_MASK |
+						 CLK_SMMUMDMA_MASK |
+						 CLK_ID_REMAPPER_MASK |
+						 CLK_G2D_MASK |
+						 CLK_SSS_MASK |
+						 CLK_MDMA_MASK |
+						 CLK_SECJTAG_MASK);
 
 	/* CLK_GATE_BUS_SYSLFT */
-	clrbits_le32(&clk->gate_bus_syslft, CLK_EFCLK_MASK);
+	clrbits_le32(&exynos_clock->gate_bus_syslft, CLK_EFCLK_MASK);
 
 	/* CLK_GATE_IP_ISP0 */
-	clrbits_le32(&clk->gate_ip_isp0, CLK_UART_ISP_MASK |
-					 CLK_WDT_ISP_MASK |
-					 CLK_PWM_ISP_MASK |
-					 CLK_MTCADC_ISP_MASK |
-					 CLK_I2C1_ISP_MASK |
-					 CLK_I2C0_ISP_MASK |
-					 CLK_MPWM_ISP_MASK |
-					 CLK_MCUCTL_ISP_MASK |
-					 CLK_INT_COMB_ISP_MASK |
-					 CLK_SMMU_MCUISP_MASK |
-					 CLK_SMMU_SCALERP_MASK |
-					 CLK_SMMU_SCALERC_MASK |
-					 CLK_SMMU_FD_MASK |
-					 CLK_SMMU_DRC_MASK |
-					 CLK_SMMU_ISP_MASK |
-					 CLK_GICISP_MASK |
-					 CLK_ARM9S_MASK |
-					 CLK_MCUISP_MASK |
-					 CLK_SCALERP_MASK |
-					 CLK_SCALERC_MASK |
-					 CLK_FD_MASK |
-					 CLK_DRC_MASK |
-					 CLK_ISP_MASK);
+	clrbits_le32(&exynos_clock->gate_ip_isp0, CLK_UART_ISP_MASK |
+						  CLK_WDT_ISP_MASK |
+						  CLK_PWM_ISP_MASK |
+						  CLK_MTCADC_ISP_MASK |
+						  CLK_I2C1_ISP_MASK |
+						  CLK_I2C0_ISP_MASK |
+						  CLK_MPWM_ISP_MASK |
+						  CLK_MCUCTL_ISP_MASK |
+						  CLK_INT_COMB_ISP_MASK |
+						  CLK_SMMU_MCUISP_MASK |
+						  CLK_SMMU_SCALERP_MASK |
+						  CLK_SMMU_SCALERC_MASK |
+						  CLK_SMMU_FD_MASK |
+						  CLK_SMMU_DRC_MASK |
+						  CLK_SMMU_ISP_MASK |
+						  CLK_GICISP_MASK |
+						  CLK_ARM9S_MASK |
+						  CLK_MCUISP_MASK |
+						  CLK_SCALERP_MASK |
+						  CLK_SCALERC_MASK |
+						  CLK_FD_MASK |
+						  CLK_DRC_MASK |
+						  CLK_ISP_MASK);
 
 	/* CLK_GATE_IP_ISP1 */
-	clrbits_le32(&clk->gate_ip_isp1, CLK_SPI1_ISP_MASK |
-					 CLK_SPI0_ISP_MASK |
-					 CLK_SMMU3DNR_MASK |
-					 CLK_SMMUDIS1_MASK |
-					 CLK_SMMUDIS0_MASK |
-					 CLK_SMMUODC_MASK |
-					 CLK_3DNR_MASK |
-					 CLK_DIS_MASK |
-					 CLK_ODC_MASK);
+	clrbits_le32(&exynos_clock->gate_ip_isp1, CLK_SPI1_ISP_MASK |
+						  CLK_SPI0_ISP_MASK |
+						  CLK_SMMU3DNR_MASK |
+						  CLK_SMMUDIS1_MASK |
+						  CLK_SMMUDIS0_MASK |
+						  CLK_SMMUODC_MASK |
+						  CLK_3DNR_MASK |
+						  CLK_DIS_MASK |
+						  CLK_ODC_MASK);
 
 	/* CLK_GATE_SCLK_ISP */
-	clrbits_le32(&clk->gate_sclk_isp, SCLK_MPWM_ISP_MASK);
+	clrbits_le32(&exynos_clock->gate_sclk_isp, SCLK_MPWM_ISP_MASK);
 
 	/* CLK_GATE_IP_GSCL */
-	clrbits_le32(&clk->gate_ip_gscl, CLK_SMMUFIMC_LITE2_MASK |
-					 CLK_SMMUFIMC_LITE1_MASK |
-					 CLK_SMMUFIMC_LITE0_MASK |
-					 CLK_SMMUGSCL3_MASK |
-					 CLK_SMMUGSCL2_MASK |
-					 CLK_SMMUGSCL1_MASK |
-					 CLK_SMMUGSCL0_MASK |
-					 CLK_GSCL_WRAP_B_MASK |
-					 CLK_GSCL_WRAP_A_MASK |
-					 CLK_CAMIF_TOP_MASK |
-					 CLK_GSCL3_MASK |
-					 CLK_GSCL2_MASK |
-					 CLK_GSCL1_MASK |
-					 CLK_GSCL0_MASK);
+	clrbits_le32(&exynos_clock->gate_ip_gscl, CLK_SMMUFIMC_LITE2_MASK |
+						  CLK_SMMUFIMC_LITE1_MASK |
+						  CLK_SMMUFIMC_LITE0_MASK |
+						  CLK_SMMUGSCL3_MASK |
+						  CLK_SMMUGSCL2_MASK |
+						  CLK_SMMUGSCL1_MASK |
+						  CLK_SMMUGSCL0_MASK |
+						  CLK_GSCL_WRAP_B_MASK |
+						  CLK_GSCL_WRAP_A_MASK |
+						  CLK_CAMIF_TOP_MASK |
+						  CLK_GSCL3_MASK |
+						  CLK_GSCL2_MASK |
+						  CLK_GSCL1_MASK |
+						  CLK_GSCL0_MASK);
 
 	/* CLK_GATE_IP_DISP1 */
-	clrbits_le32(&clk->gate_ip_disp1, CLK_SMMUTVX_MASK |
-					  CLK_ASYNCTVX_MASK |
-					  CLK_HDMI_MASK |
-					  CLK_MIXER_MASK |
-					  CLK_DSIM1_MASK);
+	clrbits_le32(&exynos_clock->gate_ip_disp1, CLK_SMMUTVX_MASK |
+						   CLK_ASYNCTVX_MASK |
+						   CLK_HDMI_MASK |
+						   CLK_MIXER_MASK |
+						   CLK_DSIM1_MASK);
 
 	/* CLK_GATE_IP_MFC */
-	clrbits_le32(&clk->gate_ip_mfc, CLK_SMMUMFCR_MASK |
-					CLK_SMMUMFCL_MASK |
-					CLK_MFC_MASK);
+	clrbits_le32(&exynos_clock->gate_ip_mfc, CLK_SMMUMFCR_MASK |
+						 CLK_SMMUMFCL_MASK |
+						 CLK_MFC_MASK);
 
 	/* CLK_GATE_IP_GEN */
-	clrbits_le32(&clk->gate_ip_gen, CLK_SMMUMDMA1_MASK |
-					CLK_SMMUJPEG_MASK |
-					CLK_SMMUROTATOR_MASK |
-					CLK_MDMA1_MASK |
-					CLK_JPEG_MASK |
-					CLK_ROTATOR_MASK);
+	clrbits_le32(&exynos_clock->gate_ip_gen, CLK_SMMUMDMA1_MASK |
+						 CLK_SMMUJPEG_MASK |
+						 CLK_SMMUROTATOR_MASK |
+						 CLK_MDMA1_MASK |
+						 CLK_JPEG_MASK |
+						 CLK_ROTATOR_MASK);
 
 	/* CLK_GATE_IP_FSYS */
-	clrbits_le32(&clk->gate_ip_fsys, CLK_WDT_IOP_MASK |
-					 CLK_SMMUMCU_IOP_MASK |
-					 CLK_SATA_PHY_I2C_MASK |
-					 CLK_SATA_PHY_CTRL_MASK |
-					 CLK_MCUCTL_MASK |
-					 CLK_NFCON_MASK |
-					 CLK_SMMURTIC_MASK |
-					 CLK_RTIC_MASK |
-					 CLK_MIPI_HSI_MASK |
-					 CLK_USBOTG_MASK |
-					 CLK_SATA_MASK |
-					 CLK_PDMA1_MASK |
-					 CLK_PDMA0_MASK |
-					 CLK_MCU_IOP_MASK);
+	clrbits_le32(&exynos_clock->gate_ip_fsys, CLK_WDT_IOP_MASK |
+						  CLK_SMMUMCU_IOP_MASK |
+						  CLK_SATA_PHY_I2C_MASK |
+						  CLK_SATA_PHY_CTRL_MASK |
+						  CLK_MCUCTL_MASK |
+						  CLK_NFCON_MASK |
+						  CLK_SMMURTIC_MASK |
+						  CLK_RTIC_MASK |
+						  CLK_MIPI_HSI_MASK |
+						  CLK_USBOTG_MASK |
+						  CLK_SATA_MASK |
+						  CLK_PDMA1_MASK |
+						  CLK_PDMA0_MASK |
+						  CLK_MCU_IOP_MASK);
 
 	/* CLK_GATE_IP_PERIC */
-	clrbits_le32(&clk->gate_ip_peric, CLK_HS_I2C3_MASK |
-					  CLK_HS_I2C2_MASK |
-					  CLK_HS_I2C1_MASK |
-					  CLK_HS_I2C0_MASK |
-					  CLK_AC97_MASK |
-					  CLK_SPDIF_MASK |
-					  CLK_PCM2_MASK |
-					  CLK_PCM1_MASK |
-					  CLK_I2S2_MASK |
-					  CLK_SPI2_MASK |
-					  CLK_SPI0_MASK);
+	clrbits_le32(&exynos_clock->gate_ip_peric, CLK_HS_I2C3_MASK |
+						   CLK_HS_I2C2_MASK |
+						   CLK_HS_I2C1_MASK |
+						   CLK_HS_I2C0_MASK |
+						   CLK_AC97_MASK |
+						   CLK_SPDIF_MASK |
+						   CLK_PCM2_MASK |
+						   CLK_PCM1_MASK |
+						   CLK_I2S2_MASK |
+						   CLK_SPI2_MASK |
+						   CLK_SPI0_MASK);
 
 	/*
 	 * CLK_GATE_IP_PERIS
@@ -416,35 +410,33 @@ void clock_gate(void)
 	 * register (PRO_ID) works correctly when the OS kernel determines
 	 * which chip it is running on.
 	 */
-	clrbits_le32(&clk->gate_ip_peris, CLK_RTC_MASK |
-					  CLK_TZPC9_MASK |
-					  CLK_TZPC8_MASK |
-					  CLK_TZPC7_MASK |
-					  CLK_TZPC6_MASK |
-					  CLK_TZPC5_MASK |
-					  CLK_TZPC4_MASK |
-					  CLK_TZPC3_MASK |
-					  CLK_TZPC2_MASK |
-					  CLK_TZPC1_MASK |
-					  CLK_TZPC0_MASK);
+	clrbits_le32(&exynos_clock->gate_ip_peris, CLK_RTC_MASK |
+						   CLK_TZPC9_MASK |
+						   CLK_TZPC8_MASK |
+						   CLK_TZPC7_MASK |
+						   CLK_TZPC6_MASK |
+						   CLK_TZPC5_MASK |
+						   CLK_TZPC4_MASK |
+						   CLK_TZPC3_MASK |
+						   CLK_TZPC2_MASK |
+						   CLK_TZPC1_MASK |
+						   CLK_TZPC0_MASK);
 
 	/* CLK_GATE_BLOCK */
-	clrbits_le32(&clk->gate_block, CLK_ACP_MASK);
+	clrbits_le32(&exynos_clock->gate_block, CLK_ACP_MASK);
 
 	/* CLK_GATE_IP_CDREX */
-	clrbits_le32(&clk->gate_ip_cdrex, CLK_DPHY0_MASK |
-					  CLK_DPHY1_MASK |
-					  CLK_TZASC_DRBXR_MASK);
+	clrbits_le32(&exynos_clock->gate_ip_cdrex, CLK_DPHY0_MASK |
+						   CLK_DPHY1_MASK |
+						   CLK_TZASC_DRBXR_MASK);
 
 }
 
 void clock_init_dp_clock(void)
 {
-	struct exynos5_clock *clk = (struct exynos5_clock *)EXYNOS5_CLOCK_BASE;
-
 	/* DP clock enable */
-	setbits_le32(&clk->gate_ip_disp1, CLK_GATE_DP1_ALLOW);
+	setbits_le32(&exynos_clock->gate_ip_disp1, CLK_GATE_DP1_ALLOW);
 
 	/* We run DP at 267 Mhz */
-	setbits_le32(&clk->div_disp1_0, CLK_DIV_DISP1_0_FIMD1);
+	setbits_le32(&exynos_clock->div_disp1_0, CLK_DIV_DISP1_0_FIMD1);
 }
diff --git a/src/cpu/samsung/exynos5250/cpu.c b/src/cpu/samsung/exynos5250/cpu.c
index 1ad248d0d1..6f20ad6fdc 100644
--- a/src/cpu/samsung/exynos5250/cpu.c
+++ b/src/cpu/samsung/exynos5250/cpu.c
@@ -59,7 +59,7 @@ static void tzpc_init(void)
 
 static void set_cpu_id(void)
 {
-	cpu_id = readl((void *)EXYNOS_PRO_ID);
+	cpu_id = readl((void *)EXYNOS5_PRO_ID);
 	cpu_id = (0xC000 | ((cpu_id & 0x00FFF000) >> 12));
 
 	/*
diff --git a/src/cpu/samsung/exynos5250/cpu.h b/src/cpu/samsung/exynos5250/cpu.h
index 4cc93916f6..12745d3d85 100644
--- a/src/cpu/samsung/exynos5250/cpu.h
+++ b/src/cpu/samsung/exynos5250/cpu.h
@@ -22,16 +22,11 @@
 
 #include <arch/io.h>
 
-#define DEVICE_NOT_AVAILABLE		0
-
-#define EXYNOS_PRO_ID			0x10000000
-
-/* EXYNOS5 */
+/* Base address registers */
 #define EXYNOS5_GPIO_PART6_BASE		0x03860000	/* Z<6:0> */
 #define EXYNOS5_PRO_ID			0x10000000
 #define EXYNOS5_CLOCK_BASE		0x10010000
 #define EXYNOS5_POWER_BASE		0x10040000
-#define EXYNOS5_SWRESET			0x10040400
 #define EXYNOS5_SYSREG_BASE		0x10050000
 #define EXYNOS5_TZPC1_DECPROT1SET	0x10110810
 #define EXYNOS5_MULTI_CORE_TIMER_BASE	0x101C0000
@@ -48,28 +43,25 @@
 #define EXYNOS5_USB_DRD_PHY_BASE	0x12100000
 #define EXYNOS5_USB_HOST_EHCI_BASE	0x12110000
 #define EXYNOS5_USB_HOST_PHY_BASE	0x12130000
-
 #define EXYNOS5_MMC_BASE		0x12200000
 #define EXYNOS5_MSHC_BASE		0x12240000
-
 #define EXYNOS5_SROMC_BASE		0x12250000
-#define EXYNOS5_UART_BASE		0x12C00000
-
-#define EXYNOS5_SPI1_BASE		0x12D30000
+#define EXYNOS5_UART0_BASE		0x12C00000
+#define EXYNOS5_UART1_BASE		0x12C10000
+#define EXYNOS5_UART2_BASE		0x12C20000
+#define EXYNOS5_UART3_BASE		0x12C30000
 #define EXYNOS5_I2C_BASE		0x12C60000
-#define EXYNOS5_SPI_BASE		0x12D20000
-#define EXYNOS5_SPI_ISP_BASE		0x131A0000
+#define EXYNOS5_SPI0_BASE		0x12D20000
+#define EXYNOS5_SPI1_BASE		0x12D30000
 #define EXYNOS5_I2S_BASE		0x12D60000
+#define EXYNOS5_UART_ISP_BASE		0x13190000
+#define EXYNOS5_SPI_ISP_BASE		0x131A0000
 #define EXYNOS5_GPIO_PART3_BASE		0x13400000	/* E00..H17 */
 #define EXYNOS5_FIMD_BASE		0x14400000
 #define EXYNOS5_DISP1_CTRL_BASE		0x14420000
 #define EXYNOS5_MIPI_DSI1_BASE		0x14500000
-
-#define EXYNOS5_ADC_BASE		DEVICE_NOT_AVAILABLE
-#define EXYNOS5_MODEM_BASE		DEVICE_NOT_AVAILABLE
-
-/* Compatibility defines */
-#define EXYNOS_POWER_BASE		EXYNOS5_POWER_BASE
+#define EXYNOS5_DP0_BASE		0x14510000
+#define EXYNOS5_DP1_BASE		0x145B0000
 
 /* Marker values stored at the bottom of IRAM stack by SPL */
 #define EXYNOS5_SPL_MARKER	0xb004f1a9	/* hexspeak word: bootflag */
@@ -102,33 +94,6 @@
  */
 #define DECPROTXSET		0xFF
 
-#define samsung_get_base_adc() ((struct exynos5_adc *)EXYNOS5_ADC_BASE)
-#define samsung_get_base_clock() ((struct exynos5_clock *)EXYNOS5_CLOCK_BASE)
-#define samsung_get_base_ace_sfr() ((struct exynos5_ace_sfr *)EXYNOS5_ACE_SFR_BASE)
-#define samsung_get_base_dsim() ((struct exynos5_dsim *)EXYNOS5_MIPI_DSI1_BASE)
-#define samsung_get_base_disp_ctrl() ((struct exynos5_disp_ctrl *)EXYNOS5_DISP1_CTRL_BASE)
-#define samsung_get_base_fimd() ((struct exynos5_fimd *)EXYNOS5_FIMD_BASE)
-#define samsung_get_base_pro_id() ((struct exynos5_pro_id *)EXYNOS5_PRO_ID)
-
-#define samsung_get_base_mmc() ((struct exynos5_mmc *)EXYNOS5_MMC_BASE)
-#define samsung_get_base_mshci() ((struct exynos5_mshci *)EXYNOS5_MSHC_BASE)
-
-#define samsung_get_base_modem() ((struct exynos5_modem *)EXYNOS5_MODEM_BASE)
-#define samsung_get_base_sromc() ((struct exynos5_sromc *)EXYNOS5_SROMC_BASE)
-#define samsung_get_base_swreset() ((struct exynos5_swreset *)EXYNOS5_SWRESET)
-#define samsung_get_base_sysreg() ((struct exynos5_sysreg *)EXYNOS5_SYSREG_BASE)
-#define samsung_get_base_uart() ((struct exynos5_uart *)EXYNOS5_UART_BASE)
-#define samsung_get_base_usb_drd_phy() ((struct exynos5_usb_drd_phy *)EXYNOS5_USB_DRD_PHY_BASE)
-#define samsung_get_base_usb_host_phy() ((struct exynos5_usb_host_phy *)EXYNOS5_USB_HOST_PHY_BASE)
-#define samsung_get_base_usb_host_otg() ((struct exynos5_usb_host_otg *)EXYNOS5_USB_HOST_OTG_BASE)
-#define samsung_get_base_watchdog() ((struct exynos5_watchdog *)EXYNOS5_WATCHDOG_BASE)
-#define samsung_get_base_power() ((struct exynos5_power *)EXYNOS5_POWER_BASE)
-#define samsung_get_base_i2s() ((struct exynos5_i2s *)EXYNOS5_I2S_BASE)
-#define samsung_get_base_spi1() ((struct exynos5_spi1 *)EXYNOS5_SPI1_BASE)
-#define samsung_get_base_i2c() ((struct exynos5_i2c *)EXYNOS5_I2C_BASE)
-#define samsung_get_base_spi() ((struct exynos5_spi *)EXYNOS5_SPI_BASE)
-#define samsung_get_base_spi_isp() ((struct exynos5_spi_isp *)EXYNOS5_SPI_ISP_BASE)
-
 #define EXYNOS5_SPI_NUM_CONTROLLERS	5
 #define EXYNOS_I2C_MAX_CONTROLLERS	8
 
diff --git a/src/cpu/samsung/exynos5250/dmc.h b/src/cpu/samsung/exynos5250/dmc.h
index acd0abbcf1..6388316c5e 100644
--- a/src/cpu/samsung/exynos5250/dmc.h
+++ b/src/cpu/samsung/exynos5250/dmc.h
@@ -19,6 +19,9 @@
 #define CPU_SAMSUNG_EXYNOS5250_DMC_H
 
 #ifndef __ASSEMBLER__
+
+#include "cpu.h"
+
 struct exynos5_dmc {
 	unsigned int concontrol;
 	unsigned int memcontrol;
@@ -113,6 +116,8 @@ struct exynos5_dmc {
 	unsigned int pmcnt3_ppc_a;
 };
 
+static struct exynos5_dmc * const exynos_dmc = (void *)EXYNOS5_DMC_CTRL_BASE;
+
 struct exynos5_phy_control {
 	unsigned int phy_con0;
 	unsigned int phy_con1;
@@ -160,6 +165,11 @@ struct exynos5_phy_control {
 	unsigned int phy_con42;
 };
 
+static struct exynos5_phy_control * const exynos_phy0_control =
+		(void *)EXYNOS5_DMC_PHY0_BASE;
+static struct exynos5_phy_control * const exynos_phy1_control =
+		(void *)EXYNOS5_DMC_PHY1_BASE;
+
 enum ddr_mode {
 	DDR_MODE_DDR2,
 	DDR_MODE_DDR3,
diff --git a/src/cpu/samsung/exynos5250/dmc_init_ddr3.c b/src/cpu/samsung/exynos5250/dmc_init_ddr3.c
index f2c228d339..89a7b613e7 100644
--- a/src/cpu/samsung/exynos5250/dmc_init_ddr3.c
+++ b/src/cpu/samsung/exynos5250/dmc_init_ddr3.c
@@ -19,9 +19,9 @@
 
 /* DDR3 mem setup file for SMDK5250 board based on EXYNOS5 */
 
-#include <console/console.h>
 #include <delay.h>
 #include <arch/io.h>
+#include <console/console.h>
 #include "clk.h"
 #include "cpu.h"
 #include "dmc.h"
@@ -31,10 +31,8 @@
 
 static void reset_phy_ctrl(void)
 {
-	struct exynos5_clock *clk = (struct exynos5_clock *)EXYNOS5_CLOCK_BASE;
-
-	writel(LPDDR3PHY_CTRL_PHY_RESET_ENABLE, &clk->lpddr3phy_ctrl);
-	writel(LPDDR3PHY_CTRL_PHY_RESET_DISABLE, &clk->lpddr3phy_ctrl);
+	writel(LPDDR3PHY_CTRL_PHY_RESET_ENABLE, &exynos_clock->lpddr3phy_ctrl);
+	writel(LPDDR3PHY_CTRL_PHY_RESET_DISABLE, &exynos_clock->lpddr3phy_ctrl);
 
 #if 0
 	/*
@@ -57,14 +55,8 @@ int ddr3_mem_ctrl_init(struct mem_timings *mem, unsigned long mem_iv_size,
 		       int mem_reset)
 {
 	unsigned int val;
-	struct exynos5_phy_control *phy0_ctrl, *phy1_ctrl;
-	struct exynos5_dmc *dmc;
 	int i;
 
-	phy0_ctrl = (struct exynos5_phy_control *)EXYNOS5_DMC_PHY0_BASE;
-	phy1_ctrl = (struct exynos5_phy_control *)EXYNOS5_DMC_PHY1_BASE;
-	dmc = (struct exynos5_dmc *)EXYNOS5_DMC_CTRL_BASE;
-
 	if (mem_reset)
 		reset_phy_ctrl();
 
@@ -73,90 +65,90 @@ int ddr3_mem_ctrl_init(struct mem_timings *mem, unsigned long mem_iv_size,
 		(mem->impedance << CA_CKE_DRVR_DS_OFFSET) |
 		(mem->impedance << CA_CS_DRVR_DS_OFFSET) |
 		(mem->impedance << CA_ADR_DRVR_DS_OFFSET);
-	writel(val, &phy0_ctrl->phy_con39);
-	writel(val, &phy1_ctrl->phy_con39);
+	writel(val, &exynos_phy0_control->phy_con39);
+	writel(val, &exynos_phy1_control->phy_con39);
 
 	/* Set Read Latency and Burst Length for PHY0 and PHY1 */
 	val = (mem->ctrl_bstlen << PHY_CON42_CTRL_BSTLEN_SHIFT) |
 		(mem->ctrl_rdlat << PHY_CON42_CTRL_RDLAT_SHIFT);
-	writel(val, &phy0_ctrl->phy_con42);
-	writel(val, &phy1_ctrl->phy_con42);
+	writel(val, &exynos_phy0_control->phy_con42);
+	writel(val, &exynos_phy1_control->phy_con42);
 
 	/* ZQ Calibration */
-	if (dmc_config_zq(mem, phy0_ctrl, phy1_ctrl)) {
+	if (dmc_config_zq(mem, exynos_phy0_control, exynos_phy1_control)){
 		printk(BIOS_EMERG, "DRAM ZQ CALIBRATION FAILURE\n");
 		return SETUP_ERR_ZQ_CALIBRATION_FAILURE;
 	}
 
 	/* DQ Signal */
-	writel(mem->phy0_pulld_dqs, &phy0_ctrl->phy_con14);
-	writel(mem->phy1_pulld_dqs, &phy1_ctrl->phy_con14);
+	writel(mem->phy0_pulld_dqs, &exynos_phy0_control->phy_con14);
+	writel(mem->phy1_pulld_dqs, &exynos_phy1_control->phy_con14);
 
 	writel(mem->concontrol | (mem->rd_fetch << CONCONTROL_RD_FETCH_SHIFT)
 		| (mem->dfi_init_start << CONCONTROL_DFI_INIT_START_SHIFT),
-		&dmc->concontrol);
+		&exynos_dmc->concontrol);
 
-	update_reset_dll(dmc, DDR_MODE_DDR3);
+	update_reset_dll(exynos_dmc, DDR_MODE_DDR3);
 
 	/* DQS Signal */
-	writel(mem->phy0_dqs, &phy0_ctrl->phy_con4);
-	writel(mem->phy1_dqs, &phy1_ctrl->phy_con4);
+	writel(mem->phy0_dqs, &exynos_phy0_control->phy_con4);
+	writel(mem->phy1_dqs, &exynos_phy1_control->phy_con4);
 
-	writel(mem->phy0_dq, &phy0_ctrl->phy_con6);
-	writel(mem->phy1_dq, &phy1_ctrl->phy_con6);
+	writel(mem->phy0_dq, &exynos_phy0_control->phy_con6);
+	writel(mem->phy1_dq, &exynos_phy1_control->phy_con6);
 
-	writel(mem->phy0_tFS, &phy0_ctrl->phy_con10);
-	writel(mem->phy1_tFS, &phy1_ctrl->phy_con10);
+	writel(mem->phy0_tFS, &exynos_phy0_control->phy_con10);
+	writel(mem->phy1_tFS, &exynos_phy1_control->phy_con10);
 
 	val = (mem->ctrl_start_point << PHY_CON12_CTRL_START_POINT_SHIFT) |
 		(mem->ctrl_inc << PHY_CON12_CTRL_INC_SHIFT) |
 		(mem->ctrl_dll_on << PHY_CON12_CTRL_DLL_ON_SHIFT) |
 		(mem->ctrl_ref << PHY_CON12_CTRL_REF_SHIFT);
-	writel(val, &phy0_ctrl->phy_con12);
-	writel(val, &phy1_ctrl->phy_con12);
+	writel(val, &exynos_phy0_control->phy_con12);
+	writel(val, &exynos_phy1_control->phy_con12);
 
 	/* Start DLL locking */
 	writel(val | (mem->ctrl_start << PHY_CON12_CTRL_START_SHIFT),
-		&phy0_ctrl->phy_con12);
+		&exynos_phy0_control->phy_con12);
 	writel(val | (mem->ctrl_start << PHY_CON12_CTRL_START_SHIFT),
-		&phy1_ctrl->phy_con12);
+		&exynos_phy1_control->phy_con12);
 
-	update_reset_dll(dmc, DDR_MODE_DDR3);
+	update_reset_dll(exynos_dmc, DDR_MODE_DDR3);
 
 	writel(mem->concontrol | (mem->rd_fetch << CONCONTROL_RD_FETCH_SHIFT),
-		&dmc->concontrol);
+		&exynos_dmc->concontrol);
 
-	/* Memory Channel Interleaving Size */
-	writel(mem->iv_size, &dmc->ivcontrol);
+	/* Memory Channel Inteleaving Size */
+	writel(mem->iv_size, &exynos_dmc->ivcontrol);
 
 	/* Set DMC MEMCONTROL register */
 	val = mem->memcontrol & ~DMC_MEMCONTROL_DSREF_ENABLE;
-	writel(val, &dmc->memcontrol);
+	writel(val, &exynos_dmc->memcontrol);
 
-	writel(mem->memconfig, &dmc->memconfig0);
-	writel(mem->memconfig, &dmc->memconfig1);
-	writel(mem->membaseconfig0, &dmc->membaseconfig0);
-	writel(mem->membaseconfig1, &dmc->membaseconfig1);
+	writel(mem->memconfig, &exynos_dmc->memconfig0);
+	writel(mem->memconfig, &exynos_dmc->memconfig1);
+	writel(mem->membaseconfig0, &exynos_dmc->membaseconfig0);
+	writel(mem->membaseconfig1, &exynos_dmc->membaseconfig1);
 
 	/* Precharge Configuration */
 	writel(mem->prechconfig_tp_cnt << PRECHCONFIG_TP_CNT_SHIFT,
-		&dmc->prechconfig);
+		&exynos_dmc->prechconfig);
 
 	/* Power Down mode Configuration */
 	writel(mem->dpwrdn_cyc << PWRDNCONFIG_DPWRDN_CYC_SHIFT |
 		mem->dsref_cyc << PWRDNCONFIG_DSREF_CYC_SHIFT,
-		&dmc->pwrdnconfig);
+		&exynos_dmc->pwrdnconfig);
 
 	/* TimingRow, TimingData, TimingPower and Timingaref
 	 * values as per Memory AC parameters
 	 */
-	writel(mem->timing_ref, &dmc->timingref);
-	writel(mem->timing_row, &dmc->timingrow);
-	writel(mem->timing_data, &dmc->timingdata);
-	writel(mem->timing_power, &dmc->timingpower);
+	writel(mem->timing_ref, &exynos_dmc->timingref);
+	writel(mem->timing_row, &exynos_dmc->timingrow);
+	writel(mem->timing_data, &exynos_dmc->timingdata);
+	writel(mem->timing_power, &exynos_dmc->timingpower);
 
 	/* Send PALL command */
-	dmc_config_prech(mem, dmc);
+	dmc_config_prech(mem, exynos_dmc);
 
 	if (mem_reset) {
 		/* Send NOP, MRS and ZQINIT commands.
@@ -164,25 +156,25 @@ int ddr3_mem_ctrl_init(struct mem_timings *mem, unsigned long mem_iv_size,
 		 * reseting the DRAM after resume, this will lead to memory
 		 * corruption as DRAM content is lost after DRAM reset
 		 */
-		dmc_config_mrs(mem, dmc);
+		dmc_config_mrs(mem, exynos_dmc);
 	}
 
 	if (mem->gate_leveling_enable) {
 		val = PHY_CON0_RESET_VAL;
 		val |= P0_CMD_EN;
-		writel(val, &phy0_ctrl->phy_con0);
-		writel(val, &phy1_ctrl->phy_con0);
+		writel(val, &exynos_phy0_control->phy_con0);
+		writel(val, &exynos_phy1_control->phy_con0);
 
 		val = PHY_CON2_RESET_VAL;
 		val |= INIT_DESKEW_EN;
-		writel(val, &phy0_ctrl->phy_con2);
-		writel(val, &phy1_ctrl->phy_con2);
+		writel(val, &exynos_phy0_control->phy_con2);
+		writel(val, &exynos_phy1_control->phy_con2);
 
 		val = PHY_CON0_RESET_VAL;
 		val |= P0_CMD_EN;
 		val |= BYTE_RDLVL_EN;
-		writel(val, &phy0_ctrl->phy_con0);
-		writel(val, &phy1_ctrl->phy_con0);
+		writel(val, &exynos_phy0_control->phy_con0);
+		writel(val, &exynos_phy1_control->phy_con0);
 
 		val = (mem->ctrl_start_point <<
 				PHY_CON12_CTRL_START_POINT_SHIFT) |
@@ -190,30 +182,30 @@ int ddr3_mem_ctrl_init(struct mem_timings *mem, unsigned long mem_iv_size,
 			(mem->ctrl_force << PHY_CON12_CTRL_FORCE_SHIFT) |
 			(mem->ctrl_start << PHY_CON12_CTRL_START_SHIFT) |
 			(mem->ctrl_ref << PHY_CON12_CTRL_REF_SHIFT);
-		writel(val, &phy0_ctrl->phy_con12);
-		writel(val, &phy1_ctrl->phy_con12);
+		writel(val, &exynos_phy0_control->phy_con12);
+		writel(val, &exynos_phy1_control->phy_con12);
 
 		val = PHY_CON2_RESET_VAL;
 		val |= INIT_DESKEW_EN;
 		val |= RDLVL_GATE_EN;
-		writel(val, &phy0_ctrl->phy_con2);
-		writel(val, &phy1_ctrl->phy_con2);
+		writel(val, &exynos_phy0_control->phy_con2);
+		writel(val, &exynos_phy1_control->phy_con2);
 
 		val = PHY_CON0_RESET_VAL;
 		val |= P0_CMD_EN;
 		val |= BYTE_RDLVL_EN;
 		val |= CTRL_SHGATE;
-		writel(val, &phy0_ctrl->phy_con0);
-		writel(val, &phy1_ctrl->phy_con0);
+		writel(val, &exynos_phy0_control->phy_con0);
+		writel(val, &exynos_phy1_control->phy_con0);
 
 		val = PHY_CON1_RESET_VAL;
 		val &= ~(CTRL_GATEDURADJ_MASK);
-		writel(val, &phy0_ctrl->phy_con1);
-		writel(val, &phy1_ctrl->phy_con1);
+		writel(val, &exynos_phy0_control->phy_con1);
+		writel(val, &exynos_phy1_control->phy_con1);
 
-		writel(CTRL_RDLVL_GATE_ENABLE, &dmc->rdlvl_config);
+		writel(CTRL_RDLVL_GATE_ENABLE, &exynos_dmc->rdlvl_config);
 		i = RDLVL_COMPLETE_TIMEOUT;
-		while ((readl(&dmc->phystatus) &
+		while ((readl(&exynos_dmc->phystatus) &
 			(RDLVL_COMPLETE_CHO | RDLVL_COMPLETE_CH1)) !=
 			(RDLVL_COMPLETE_CHO | RDLVL_COMPLETE_CH1) && i > 0) {
 			/*
@@ -227,10 +219,10 @@ int ddr3_mem_ctrl_init(struct mem_timings *mem, unsigned long mem_iv_size,
 			printk(BIOS_EMERG, "Timeout on RDLVL. No DRAM.\n");
 			return SETUP_ERR_RDLV_COMPLETE_TIMEOUT;
 		}
-		writel(CTRL_RDLVL_GATE_DISABLE, &dmc->rdlvl_config);
+		writel(CTRL_RDLVL_GATE_DISABLE, &exynos_dmc->rdlvl_config);
 
-		writel(0, &phy0_ctrl->phy_con14);
-		writel(0, &phy1_ctrl->phy_con14);
+		writel(0, &exynos_phy0_control->phy_con14);
+		writel(0, &exynos_phy1_control->phy_con14);
 
 		val = (mem->ctrl_start_point <<
 				PHY_CON12_CTRL_START_POINT_SHIFT) |
@@ -239,19 +231,20 @@ int ddr3_mem_ctrl_init(struct mem_timings *mem, unsigned long mem_iv_size,
 			(mem->ctrl_start << PHY_CON12_CTRL_START_SHIFT) |
 			(mem->ctrl_dll_on << PHY_CON12_CTRL_DLL_ON_SHIFT) |
 			(mem->ctrl_ref << PHY_CON12_CTRL_REF_SHIFT);
-		writel(val, &phy0_ctrl->phy_con12);
-		writel(val, &phy1_ctrl->phy_con12);
+		writel(val, &exynos_phy0_control->phy_con12);
+		writel(val, &exynos_phy1_control->phy_con12);
 
-		update_reset_dll(dmc, DDR_MODE_DDR3);
+		update_reset_dll(exynos_dmc, DDR_MODE_DDR3);
 	}
 
 	/* Send PALL command */
-	dmc_config_prech(mem, dmc);
+	dmc_config_prech(mem, exynos_dmc);
 
-	writel(mem->memcontrol, &dmc->memcontrol);
+	writel(mem->memcontrol, &exynos_dmc->memcontrol);
 
 	/* Set DMC Concontrol and enable auto-refresh counter */
 	writel(mem->concontrol | (mem->rd_fetch << CONCONTROL_RD_FETCH_SHIFT)
-		| (mem->aref_en << CONCONTROL_AREF_EN_SHIFT), &dmc->concontrol);
+		| (mem->aref_en << CONCONTROL_AREF_EN_SHIFT),
+		&exynos_dmc->concontrol);
 	return 0;
 }
diff --git a/src/cpu/samsung/exynos5250/dp.h b/src/cpu/samsung/exynos5250/dp.h
index 5c778bae47..b1533c74f7 100644
--- a/src/cpu/samsung/exynos5250/dp.h
+++ b/src/cpu/samsung/exynos5250/dp.h
@@ -163,6 +163,10 @@ struct exynos5_dp {
 	u8	res21[0x3c];
 	u32	soc_general_ctl;
 };
+
+static struct exynos5_dp * const exynos_dp0 = (void *)EXYNOS5_DP0_BASE;
+static struct exynos5_dp * const exynos_dp1 = (void *)EXYNOS5_DP1_BASE;
+
 /* DP_TX_SW_RESET */
 #define RESET_DP_TX				(1 << 0)
 
diff --git a/src/cpu/samsung/exynos5250/fb.c b/src/cpu/samsung/exynos5250/fb.c
index 3724a247c6..080be49250 100644
--- a/src/cpu/samsung/exynos5250/fb.c
+++ b/src/cpu/samsung/exynos5250/fb.c
@@ -20,22 +20,19 @@
 
 /* LCD driver for Exynos */
 
-#include <arch/io.h>
+#include <delay.h>
 #include <stdlib.h>
 #include <string.h>
 #include <timer.h>
-#include <delay.h>
+#include <arch/io.h>
 #include <console/console.h>
-#include "cpu.h"
 #include "power.h"
 #include "sysreg.h"
-#include <drivers/maxim/max77686/max77686.h>
 
-#include "device/i2c.h"
-#include "i2c.h"
-#include "fimd.h"
 #include "dp.h"
 #include "dp-core.h"
+#include "fimd.h"
+#include "i2c.h"
 
 /*
  * Here is the rough outline of how we bring up the display:
@@ -109,10 +106,8 @@ short console_row;
 /* Bypass FIMD of DISP1_BLK */
 static void fimd_bypass(void)
 {
-	struct exynos5_sysreg *sysreg = samsung_get_base_sysreg();
-
-	setbits_le32(&sysreg->disp1blk_cfg, FIMDBYPASS_DISP1);
-	sysreg->disp1blk_cfg &= ~FIMDBYPASS_DISP1;
+	setbits_le32(&exynos_sysreg->disp1blk_cfg, FIMDBYPASS_DISP1);
+	exynos_sysreg->disp1blk_cfg &= ~FIMDBYPASS_DISP1;
 }
 
 /*
@@ -125,56 +120,52 @@ void fb_init(unsigned long int fb_size, void *lcdbase,
 	     struct exynos5_fimd_panel *pd)
 {
 	unsigned int val;
-	struct exynos5_fimd *fimd = samsung_get_base_fimd();
-	struct exynos5_disp_ctrl *disp_ctrl = samsung_get_base_disp_ctrl();
 
 	fb_size = ALIGN(fb_size, 4096);
 
-	writel(pd->ivclk | pd->fixvclk, &disp_ctrl->vidcon1);
+	writel(pd->ivclk | pd->fixvclk, &exynos_disp_ctrl->vidcon1);
 	val = ENVID_ON | ENVID_F_ON | (pd->clkval_f << CLKVAL_F_OFFSET);
-	writel(val, &fimd->vidcon0);
+	writel(val, &exynos_fimd->vidcon0);
 
 	val = (pd->vsync << VSYNC_PULSE_WIDTH_OFFSET) |
 		(pd->lower_margin << V_FRONT_PORCH_OFFSET) |
 		(pd->upper_margin << V_BACK_PORCH_OFFSET);
-	writel(val, &disp_ctrl->vidtcon0);
+	writel(val, &exynos_disp_ctrl->vidtcon0);
 
 	val = (pd->hsync << HSYNC_PULSE_WIDTH_OFFSET) |
 		(pd->right_margin << H_FRONT_PORCH_OFFSET) |
 		(pd->left_margin << H_BACK_PORCH_OFFSET);
-	writel(val, &disp_ctrl->vidtcon1);
+	writel(val, &exynos_disp_ctrl->vidtcon1);
 
 	val = ((pd->xres - 1) << HOZVAL_OFFSET) |
 		((pd->yres - 1) << LINEVAL_OFFSET);
-	writel(val, &disp_ctrl->vidtcon2);
+	writel(val, &exynos_disp_ctrl->vidtcon2);
 
-	writel((unsigned int)lcdbase, &fimd->vidw00add0b0);
-	writel((unsigned int)lcdbase + fb_size, &fimd->vidw00add1b0);
+	writel((unsigned int)lcdbase, &exynos_fimd->vidw00add0b0);
+	writel((unsigned int)lcdbase + fb_size, &exynos_fimd->vidw00add1b0);
 
-	writel(pd->xres * 2, &fimd->vidw00add2);
+	writel(pd->xres * 2, &exynos_fimd->vidw00add2);
 
 	val = ((pd->xres - 1) << OSD_RIGHTBOTX_F_OFFSET);
 	val |= ((pd->yres - 1) << OSD_RIGHTBOTY_F_OFFSET);
-	writel(val, &fimd->vidosd0b);
-	writel(pd->xres * pd->yres, &fimd->vidosd0c);
+	writel(val, &exynos_fimd->vidosd0b);
+	writel(pd->xres * pd->yres, &exynos_fimd->vidosd0c);
 
-	setbits_le32(&fimd->shadowcon, CHANNEL0_EN);
+	setbits_le32(&exynos_fimd->shadowcon, CHANNEL0_EN);
 
 	val = BPPMODE_F_RGB_16BIT_565 << BPPMODE_F_OFFSET;
 	val |= ENWIN_F_ENABLE | HALF_WORD_SWAP_EN;
-	writel(val, &fimd->wincon0);
+	writel(val, &exynos_fimd->wincon0);
 
 	/* DPCLKCON_ENABLE */
-	writel(1 << 1, &fimd->dpclkcon);
+	writel(1 << 1, &exynos_fimd->dpclkcon);
 }
 
 #ifdef UNUSED_CODE
 void exynos_fimd_disable(void)
 {
-	struct exynos5_fimd *fimd = samsung_get_base_fimd();
-
-	writel(0, &fimd->wincon0);
-	clrbits_le32(&fimd->shadowcon, CHANNEL0_EN);
+	writel(0, &exynos_fimd->wincon0);
+	clrbits_le32(&exynos_fimd->shadowcon, CHANNEL0_EN);
 }
 #endif
 
diff --git a/src/cpu/samsung/exynos5250/fimd.h b/src/cpu/samsung/exynos5250/fimd.h
index f3dea37a1b..178fb73d08 100644
--- a/src/cpu/samsung/exynos5250/fimd.h
+++ b/src/cpu/samsung/exynos5250/fimd.h
@@ -22,6 +22,8 @@
 #ifndef CPU_SAMSUNG_EXYNOS5250_FIMD_H
 #define CPU_SAMSUNG_EXYNOS5250_FIMD_H
 
+#include "cpu.h"
+
 /* FIMD register map */
 struct exynos5_fimd {
 	/* This is an incomplete list. Add registers as and when required */
@@ -60,6 +62,8 @@ struct exynos5_fimd {
 	unsigned int dpclkcon;
 };
 
+static struct exynos5_fimd * const exynos_fimd = (void *)EXYNOS5_FIMD_BASE;
+
 #define W0_SHADOW_PROTECT	(0x1 << 10)
 #define COMPKEY_F		0xffffff
 #define ENVID_F_ON		(0x1 << 0)
@@ -106,6 +110,9 @@ struct exynos5_disp_ctrl {
 	unsigned int trigcon;
 };
 
+static struct exynos5_disp_ctrl * const exynos_disp_ctrl =
+		(void *)EXYNOS5_DISP1_CTRL_BASE;
+
 #define VCLK_RISING_EDGE		(1 << 7)
 #define VCLK_RUNNING			(1 << 9)
 
diff --git a/src/cpu/samsung/exynos5250/gpio.h b/src/cpu/samsung/exynos5250/gpio.h
index 0b97526f08..a8f22f7df0 100644
--- a/src/cpu/samsung/exynos5250/gpio.h
+++ b/src/cpu/samsung/exynos5250/gpio.h
@@ -20,6 +20,8 @@
 #ifndef CPU_SAMSUNG_EXYNOS5250_GPIO_H
 #define CPU_SAMSUNG_EXYNOS5250_GPIO_H
 
+#include "cpu.h"
+
 struct gpio_bank {
 	unsigned int	con;
 	unsigned int	dat;
@@ -52,71 +54,58 @@ struct gpio_bank {
 #define GPIO_DRV_FAST	0x0
 #define GPIO_DRV_SLOW	0x1
 
-#define EXYNOS5_GPIO_BASE0	0x11400000
-#define EXYNOS5_GPIO_BASE1	0x13400000
-#define EXYNOS5_GPIO_BASE2	0x10d10000
-#define EXYNOS5_GPIO_BASE3	0x03860000
-
 enum exynos5_gpio_port {
-	/*
-	 * Ordered by base address + offset.
-	 * ETC registers are special, thus not included.
-	 */
-
-	/* base == EXYNOS_GPIO_BASE0 */
-	EXYNOS5_GPA0 = EXYNOS5_GPIO_BASE0 + 0x0000,
-	EXYNOS5_GPA1 = EXYNOS5_GPIO_BASE0 + 0x0020,
-	EXYNOS5_GPA2 = EXYNOS5_GPIO_BASE0 + 0x0040,
-
-	EXYNOS5_GPB0 = EXYNOS5_GPIO_BASE0 + 0x0060,
-	EXYNOS5_GPB1 = EXYNOS5_GPIO_BASE0 + 0x0080,
-	EXYNOS5_GPB2 = EXYNOS5_GPIO_BASE0 + 0x00a0,
-	EXYNOS5_GPB3 = EXYNOS5_GPIO_BASE0 + 0x00c0,
-
-	EXYNOS5_GPC0 = EXYNOS5_GPIO_BASE0 + 0x00e0,
-	EXYNOS5_GPC1 = EXYNOS5_GPIO_BASE0 + 0x0100,
-	EXYNOS5_GPC2 = EXYNOS5_GPIO_BASE0 + 0x0120,
-	EXYNOS5_GPC3 = EXYNOS5_GPIO_BASE0 + 0x0140,
-
-	EXYNOS5_GPD0 = EXYNOS5_GPIO_BASE0 + 0x0160,
-	EXYNOS5_GPD1 = EXYNOS5_GPIO_BASE0 + 0x0180,
-
-	EXYNOS5_GPY0 = EXYNOS5_GPIO_BASE0 + 0x01a0,
-	EXYNOS5_GPY1 = EXYNOS5_GPIO_BASE0 + 0x01c0,
-	EXYNOS5_GPY2 = EXYNOS5_GPIO_BASE0 + 0x01e0,
-	EXYNOS5_GPY3 = EXYNOS5_GPIO_BASE0 + 0x0200,
-	EXYNOS5_GPY4 = EXYNOS5_GPIO_BASE0 + 0x0220,
-	EXYNOS5_GPY5 = EXYNOS5_GPIO_BASE0 + 0x0240,
-	EXYNOS5_GPY6 = EXYNOS5_GPIO_BASE0 + 0x0260,
-
-	EXYNOS5_GPX0 = EXYNOS5_GPIO_BASE0 + 0x0c00,
-	EXYNOS5_GPX1 = EXYNOS5_GPIO_BASE0 + 0x0c20,
-	EXYNOS5_GPX2 = EXYNOS5_GPIO_BASE0 + 0x0c40,
-	EXYNOS5_GPX3 = EXYNOS5_GPIO_BASE0 + 0x0c60,
-
-	/* base == EXYNOS_GPIO_BASE1 */
-	EXYNOS5_GPE0 = EXYNOS5_GPIO_BASE1 + 0x0000,
-	EXYNOS5_GPE1 = EXYNOS5_GPIO_BASE1 + 0x0020,
-
-	EXYNOS5_GPF0 = EXYNOS5_GPIO_BASE1 + 0x0040,
-	EXYNOS5_GPF1 = EXYNOS5_GPIO_BASE1 + 0x0060,
-
-	EXYNOS5_GPG0 = EXYNOS5_GPIO_BASE1 + 0x0080,
-	EXYNOS5_GPG1 = EXYNOS5_GPIO_BASE1 + 0x00a0,
-	EXYNOS5_GPG2 = EXYNOS5_GPIO_BASE1 + 0x00c0,
-
-	EXYNOS5_GPH0 = EXYNOS5_GPIO_BASE1 + 0x00e0,
-	EXYNOS5_GPH1 = EXYNOS5_GPIO_BASE1 + 0x0100,
-
-	/* base == EXYNOS_GPIO_BASE2 */
-	EXYNOS5_GPV0 = EXYNOS5_GPIO_BASE2 + 0x0000,
-	EXYNOS5_GPV1 = EXYNOS5_GPIO_BASE2 + 0x0020,
-	EXYNOS5_GPV2 = EXYNOS5_GPIO_BASE2 + 0x0060,
-	EXYNOS5_GPV3 = EXYNOS5_GPIO_BASE2 + 0x0080,
-	EXYNOS5_GPV4 = EXYNOS5_GPIO_BASE2 + 0x00c0,
-
-	/* base == EXYNOS_GPIO_BASE3 */
-	EXYNOS5_GPZ = EXYNOS5_GPIO_BASE3 + 0x0000,
+	EXYNOS5_GPA0 = EXYNOS5_GPIO_PART1_BASE + 0x0000,
+	EXYNOS5_GPA1 = EXYNOS5_GPIO_PART1_BASE + 0x0020,
+	EXYNOS5_GPA2 = EXYNOS5_GPIO_PART1_BASE + 0x0040,
+
+	EXYNOS5_GPB0 = EXYNOS5_GPIO_PART1_BASE + 0x0060,
+	EXYNOS5_GPB1 = EXYNOS5_GPIO_PART1_BASE + 0x0080,
+	EXYNOS5_GPB2 = EXYNOS5_GPIO_PART1_BASE + 0x00a0,
+	EXYNOS5_GPB3 = EXYNOS5_GPIO_PART1_BASE + 0x00c0,
+
+	EXYNOS5_GPC0 = EXYNOS5_GPIO_PART1_BASE + 0x00e0,
+	EXYNOS5_GPC1 = EXYNOS5_GPIO_PART1_BASE + 0x0100,
+	EXYNOS5_GPC2 = EXYNOS5_GPIO_PART1_BASE + 0x0120,
+	EXYNOS5_GPC3 = EXYNOS5_GPIO_PART1_BASE + 0x0140,
+
+	EXYNOS5_GPD0 = EXYNOS5_GPIO_PART1_BASE + 0x0160,
+	EXYNOS5_GPD1 = EXYNOS5_GPIO_PART1_BASE + 0x0180,
+
+	EXYNOS5_GPY0 = EXYNOS5_GPIO_PART1_BASE + 0x01a0,
+	EXYNOS5_GPY1 = EXYNOS5_GPIO_PART1_BASE + 0x01c0,
+	EXYNOS5_GPY2 = EXYNOS5_GPIO_PART1_BASE + 0x01e0,
+	EXYNOS5_GPY3 = EXYNOS5_GPIO_PART1_BASE + 0x0200,
+	EXYNOS5_GPY4 = EXYNOS5_GPIO_PART1_BASE + 0x0220,
+	EXYNOS5_GPY5 = EXYNOS5_GPIO_PART1_BASE + 0x0240,
+	EXYNOS5_GPY6 = EXYNOS5_GPIO_PART1_BASE + 0x0260,
+
+	EXYNOS5_GPX0 = EXYNOS5_GPIO_PART2_BASE + 0x0000,
+	EXYNOS5_GPX1 = EXYNOS5_GPIO_PART2_BASE + 0x0020,
+	EXYNOS5_GPX2 = EXYNOS5_GPIO_PART2_BASE + 0x0040,
+	EXYNOS5_GPX3 = EXYNOS5_GPIO_PART2_BASE + 0x0060,
+
+	EXYNOS5_GPE0 = EXYNOS5_GPIO_PART3_BASE + 0x0000,
+	EXYNOS5_GPE1 = EXYNOS5_GPIO_PART3_BASE + 0x0020,
+
+	EXYNOS5_GPF0 = EXYNOS5_GPIO_PART3_BASE + 0x0040,
+	EXYNOS5_GPF1 = EXYNOS5_GPIO_PART3_BASE + 0x0060,
+
+	EXYNOS5_GPG0 = EXYNOS5_GPIO_PART3_BASE + 0x0080,
+	EXYNOS5_GPG1 = EXYNOS5_GPIO_PART3_BASE + 0x00a0,
+	EXYNOS5_GPG2 = EXYNOS5_GPIO_PART3_BASE + 0x00c0,
+
+	EXYNOS5_GPH0 = EXYNOS5_GPIO_PART3_BASE + 0x00e0,
+	EXYNOS5_GPH1 = EXYNOS5_GPIO_PART3_BASE + 0x0100,
+
+	EXYNOS5_GPV0 = EXYNOS5_GPIO_PART4_BASE + 0x0000,
+	EXYNOS5_GPV1 = EXYNOS5_GPIO_PART4_BASE + 0x0020,
+	EXYNOS5_GPV2 = EXYNOS5_GPIO_PART4_BASE + 0x0060,
+	EXYNOS5_GPV3 = EXYNOS5_GPIO_PART4_BASE + 0x0080,
+
+	EXYNOS5_GPV4 = EXYNOS5_GPIO_PART5_BASE + 0x0000,
+
+	EXYNOS5_GPZ = EXYNOS5_GPIO_PART6_BASE + 0x0000,
 };
 
 enum {
diff --git a/src/cpu/samsung/exynos5250/mct.c b/src/cpu/samsung/exynos5250/mct.c
index 4c5cdd1b20..b02fc6d9fa 100644
--- a/src/cpu/samsung/exynos5250/mct.c
+++ b/src/cpu/samsung/exynos5250/mct.c
@@ -21,84 +21,25 @@
 #include <arch/io.h>
 #include "clk.h"
 
-struct __attribute__((packed)) mct_regs
-{
-	uint32_t mct_cfg;
-	uint8_t reserved0[0xfc];
-	uint32_t g_cnt_l;
-	uint32_t g_cnt_u;
-	uint8_t reserved1[0x8];
-	uint32_t g_cnt_wstat;
-	uint8_t reserved2[0xec];
-	uint32_t g_comp0_l;
-	uint32_t g_comp0_u;
-	uint32_t g_comp0_addr_incr;
-	uint8_t reserved3[0x4];
-	uint32_t g_comp1_l;
-	uint32_t g_comp1_u;
-	uint32_t g_comp1_addr_incr;
-	uint8_t reserved4[0x4];
-	uint32_t g_comp2_l;
-	uint32_t g_comp2_u;
-	uint32_t g_comp2_addr_incr;
-	uint8_t reserved5[0x4];
-	uint32_t g_comp3_l;
-	uint32_t g_comp3_u;
-	uint32_t g_comp3_addr_incr;
-	uint8_t reserved6[0x4];
-	uint32_t g_tcon;
-	uint32_t g_int_cstat;
-	uint32_t g_int_enb;
-	uint32_t g_wstat;
-	uint8_t reserved7[0xb0];
-	uint32_t l0_tcntb;
-	uint32_t l0_tcnto;
-	uint32_t l0_icntb;
-	uint32_t l0_icnto;
-	uint32_t l0_frcntb;
-	uint32_t l0_frcnto;
-	uint8_t reserved8[0x8];
-	uint32_t l0_tcon;
-	uint8_t reserved9[0xc];
-	uint32_t l0_int_cstat;
-	uint32_t l0_int_enb;
-	uint8_t reserved10[0x8];
-	uint32_t l0_wstat;
-	uint8_t reserved11[0xbc];
-	uint32_t l1_tcntb;
-	uint32_t l1_tcnto;
-	uint32_t l1_icntb;
-	uint32_t l1_icnto;
-	uint32_t l1_frcntb;
-	uint32_t l1_frcnto;
-	uint8_t reserved12[0x8];
-	uint32_t l1_tcon;
-	uint8_t reserved13[0xc];
-	uint32_t l1_int_cstat;
-	uint32_t l1_int_enb;
-	uint8_t reserved14[0x8];
-	uint32_t l1_wstat;
-};
-
 static int enabled = 0;
-static struct mct_regs *const mct =
-	(struct mct_regs *)MCT_ADDRESS;
 
 uint64_t mct_raw_value(void)
 {
 	if (!enabled) {
-		writel(readl(&mct->g_tcon) | (0x1 << 8), &mct->g_tcon);
+		writel(readl(&exynos_mct->g_tcon) | (0x1 << 8),
+			&exynos_mct->g_tcon);
 		enabled = 1;
 	}
 
-	uint64_t upper = readl(&mct->g_cnt_u);
-	uint64_t lower = readl(&mct->g_cnt_l);
+	uint64_t upper = readl(&exynos_mct->g_cnt_u);
+	uint64_t lower = readl(&exynos_mct->g_cnt_l);
 
 	return (upper << 32) | lower;
 }
 
 void mct_start(void)
 {
-	writel(readl(&mct->g_tcon) | (0x1 << 8), &mct->g_tcon);
+	writel(readl(&exynos_mct->g_tcon) | (0x1 << 8),
+		&exynos_mct->g_tcon);
 	enabled = 1;
 }
diff --git a/src/cpu/samsung/exynos5250/pinmux.c b/src/cpu/samsung/exynos5250/pinmux.c
index 89ce23ef69..dc9590f20f 100644
--- a/src/cpu/samsung/exynos5250/pinmux.c
+++ b/src/cpu/samsung/exynos5250/pinmux.c
@@ -20,7 +20,6 @@
 #include <console/console.h>
 #include <assert.h>
 #include "gpio.h"
-#include "cpu.h"
 #include "pinmux.h"
 
 static void exynos_pinmux_uart(int start, int count)
diff --git a/src/cpu/samsung/exynos5250/power.c b/src/cpu/samsung/exynos5250/power.c
index be055e35dd..e873129f64 100644
--- a/src/cpu/samsung/exynos5250/power.c
+++ b/src/cpu/samsung/exynos5250/power.c
@@ -19,75 +19,56 @@
 
 /* Power setup code for EXYNOS5 */
 
-#include <console/console.h>
 #include <arch/io.h>
 #include <arch/hlt.h>
-#include "cpu.h"
+#include <console/console.h>
 #include "power.h"
 
 static void ps_hold_setup(void)
 {
-	struct exynos5_power *power =
-		samsung_get_base_power();
-
 	/* Set PS-Hold high */
-	setbits_le32(&power->ps_hold_ctrl, POWER_PS_HOLD_CONTROL_DATA_HIGH);
+	setbits_le32(&exynos_power->ps_hold_ctrl,
+		     POWER_PS_HOLD_CONTROL_DATA_HIGH);
 }
 
 void power_reset(void)
 {
-	struct exynos5_power *power =
-		samsung_get_base_power();
-
 	/* Clear inform1 so there's no change we think we've got a wake reset */
-	power->inform1 = 0;
+	exynos_power->inform1 = 0;
 
-	setbits_le32(&power->sw_reset, 1);
+	setbits_le32(&exynos_power->sw_reset, 1);
 }
 
 /* This function never returns */
 void power_shutdown(void)
 {
-	struct exynos5_power *power =
-		samsung_get_base_power();
-
-	clrbits_le32(&power->ps_hold_ctrl, POWER_PS_HOLD_CONTROL_DATA_HIGH);
+	clrbits_le32(&exynos_power->ps_hold_ctrl,
+		     POWER_PS_HOLD_CONTROL_DATA_HIGH);
 
 	hlt();
 }
 
 void power_enable_dp_phy(void)
 {
-	struct exynos5_power *power =
-		samsung_get_base_power();
-
-	setbits_le32(&power->dptx_phy_control, DPTX_PHY_ENABLE);
+	setbits_le32(&exynos_power->dptx_phy_control, DPTX_PHY_ENABLE);
 }
 
 void power_enable_hw_thermal_trip(void)
 {
-	struct exynos5_power *power =
-		samsung_get_base_power();
-
 	/* Enable HW thermal trip */
-	setbits_le32(&power->ps_hold_ctrl, POWER_ENABLE_HW_TRIP);
+	setbits_le32(&exynos_power->ps_hold_ctrl, POWER_ENABLE_HW_TRIP);
 }
 
 uint32_t power_read_reset_status(void)
 {
-	struct exynos5_power *power =
-		samsung_get_base_power();
-
-	return power->inform1;
+	return exynos_power->inform1;
 }
 
 void power_exit_wakeup(void)
 {
-	struct exynos5_power *power =
-		samsung_get_base_power();
 	typedef void (*resume_func)(void);
 
-	((resume_func)power->inform0)();
+	((resume_func)exynos_power->inform0)();
 }
 
 int power_init(void)
@@ -98,10 +79,7 @@ int power_init(void)
 
 void power_enable_xclkout(void)
 {
-	struct exynos5_power *power =
-		samsung_get_base_power();
-
 	/* use xxti for xclk out */
-	clrsetbits_le32(&power->pmu_debug, PMU_DEBUG_CLKOUT_SEL_MASK,
+	clrsetbits_le32(&exynos_power->pmu_debug, PMU_DEBUG_CLKOUT_SEL_MASK,
 				PMU_DEBUG_XXTI);
 }
diff --git a/src/cpu/samsung/exynos5250/power.h b/src/cpu/samsung/exynos5250/power.h
index 2b57e18ec4..293fe3b704 100644
--- a/src/cpu/samsung/exynos5250/power.h
+++ b/src/cpu/samsung/exynos5250/power.h
@@ -22,6 +22,8 @@
 #ifndef CPU_SAMSUNG_EXYNOS5250_POWER_H
 #define CPU_SAMSUNG_EXYNOS5250_POWER_H
 
+#include "cpu.h"
+
 /* Enable HW thermal trip with PS_HOLD_CONTROL register ENABLE_HW_TRIP bit */
 void power_enable_hw_thermal_trip(void);
 
@@ -60,6 +62,8 @@ struct exynos5_power {
 	uint32_t	ps_hold_ctrl;		/* 0x330c */
 } __attribute__ ((__packed__));
 
+static struct exynos5_power * const exynos_power = (void*)EXYNOS5_POWER_BASE;
+
 /**
  * Perform a software reset.
  */
diff --git a/src/cpu/samsung/exynos5250/spi.c b/src/cpu/samsung/exynos5250/spi.c
index e8b68b40ea..33ec6984db 100644
--- a/src/cpu/samsung/exynos5250/spi.c
+++ b/src/cpu/samsung/exynos5250/spi.c
@@ -18,17 +18,14 @@
  * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
  */
 
-#include <console/console.h>
-#include <arch/io.h>
-#include <stdlib.h>
 #include <assert.h>
-#include "gpio.h"
+#include <stdlib.h>
+#include <arch/io.h>
+#include <console/console.h>
 #include "clk.h"
+#include "gpio.h"
 #include "spi.h"
 
-#define OM_STAT		(0x1f << 1)
-#define EXYNOS_BASE_SPI1 ((void *)0x12d30000)
-
 #if defined(CONFIG_DEBUG_SPI) && CONFIG_DEBUG_SPI
 # define DEBUG_SPI(x,...)	printk(BIOS_DEBUG, "EXYNOS_SPI: " x)
 #else
@@ -201,7 +198,7 @@ int initialize_exynos_spi_cbfs_media(struct cbfs_media *media,
 	static struct exynos_spi_media context;
 	DEBUG_SPI("initialize_exynos_spi_cbfs_media\n");
 
-	context.regs = EXYNOS_BASE_SPI1;
+	context.regs = (void*)EXYNOS5_SPI1_BASE;
 	context.buffer.allocated = context.buffer.last_allocate = 0;
 	context.buffer.buffer = buffer_address;
 	context.buffer.size = buffer_size;
diff --git a/src/cpu/samsung/exynos5250/sysreg.h b/src/cpu/samsung/exynos5250/sysreg.h
index 570ee6c1dd..1362177a33 100644
--- a/src/cpu/samsung/exynos5250/sysreg.h
+++ b/src/cpu/samsung/exynos5250/sysreg.h
@@ -22,6 +22,8 @@
 #ifndef CPU_SAMSUNG_EXYNOS5250_SYSREG_H
 #define CPU_SAMSUNG_EXYNOS5250_SYSREG_H
 
+#include "cpu.h"
+
 /* sysreg map */
 struct exynos5_sysreg {
 	/* Add registers as and when required */
@@ -31,6 +33,9 @@ struct exynos5_sysreg {
 	unsigned int	usb20_phy_cfg;
 };
 
+static struct exynos5_sysreg * const exynos_sysreg =
+		(void *)EXYNOS5_SYSREG_BASE;
+
 #define FIMDBYPASS_DISP1	(1 << 15)
 #define USB20_PHY_CFG_EN	(1 << 0)
 
diff --git a/src/cpu/samsung/exynos5250/uart.c b/src/cpu/samsung/exynos5250/uart.c
index a73a01aba7..cc97291807 100644
--- a/src/cpu/samsung/exynos5250/uart.c
+++ b/src/cpu/samsung/exynos5250/uart.c
@@ -17,6 +17,7 @@
  * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
  */
 
+#include <types.h>
 #include <console/uart.h>
 #include <arch/io.h>
 #include <boot/coreboot_tables.h>
@@ -24,6 +25,7 @@
 #include "clk.h"
 #include "cpu.h"
 #include "periph.h"
+#include "uart.h"
 
 #define RX_FIFO_COUNT_MASK	0xff
 #define RX_FIFO_FULL_MASK	(1 << 8)
diff --git a/src/cpu/samsung/exynos5250/uart.h b/src/cpu/samsung/exynos5250/uart.h
index 466ff404de..d324a2f93d 100644
--- a/src/cpu/samsung/exynos5250/uart.h
+++ b/src/cpu/samsung/exynos5250/uart.h
@@ -21,12 +21,6 @@
 #ifndef CPU_SAMSUNG_EXYNOS5250_UART_H
 #define CPU_SAMSUNG_EXYNOS5250_UART_H
 
-#define EXYNOS5_UART0_BASE	0x12c00000
-#define EXYNOS5_UART1_BASE	0x12c10000
-#define EXYNOS5_UART2_BASE	0x12c20000
-#define EXYNOS5_UART3_BASE	0x12c30000
-#define EXYNOS5_ISP_UART_BASE	0x13190000
-
 /* baudrate rest value */
 union br_rest {
 	unsigned short	slot;		/* udivslot */
diff --git a/src/cpu/samsung/exynos5250/usb.c b/src/cpu/samsung/exynos5250/usb.c
index 9e990a1137..521ea4da5a 100644
--- a/src/cpu/samsung/exynos5250/usb.c
+++ b/src/cpu/samsung/exynos5250/usb.c
@@ -22,7 +22,6 @@
 #include <arch/io.h>
 #include <console/console.h>
 #include <device/device.h>
-#include "cpu.h"
 #include "gpio.h"
 #include "power.h"
 #include "sysreg.h"
@@ -31,17 +30,15 @@
 void setup_usb_host_phy(int hsic_gpio)
 {
 	unsigned int hostphy_ctrl0;
-	struct exynos5_sysreg *sysreg = samsung_get_base_sysreg();
-	struct exynos5_power *power = samsung_get_base_power();
-	struct exynos5_usb_host_phy *phy = samsung_get_base_usb_host_phy();
 
-	setbits_le32(&sysreg->usb20_phy_cfg, USB20_PHY_CFG_EN);
-	setbits_le32(&power->usb_host_phy_ctrl, POWER_USB_HOST_PHY_CTRL_EN);
+	setbits_le32(&exynos_sysreg->usb20_phy_cfg, USB20_PHY_CFG_EN);
+	setbits_le32(&exynos_power->usb_host_phy_ctrl,
+		     POWER_USB_HOST_PHY_CTRL_EN);
 
 	printk(BIOS_DEBUG, "Powering up USB HOST PHY (%s HSIC)\n",
 			hsic_gpio ? "with" : "without");
 
-	hostphy_ctrl0 = readl(&phy->usbphyctrl0);
+	hostphy_ctrl0 = readl(&exynos_usb_host_phy->usbphyctrl0);
 	hostphy_ctrl0 &= ~(HOST_CTRL0_FSEL_MASK |
 			   HOST_CTRL0_COMMONON_N |
 			   /* HOST Phy setting */
@@ -55,15 +52,15 @@ void setup_usb_host_phy(int hsic_gpio)
 			  /* HOST Phy setting */
 			  HOST_CTRL0_LINKSWRST |
 			  HOST_CTRL0_UTMISWRST);
-	writel(hostphy_ctrl0, &phy->usbphyctrl0);
+	writel(hostphy_ctrl0, &exynos_usb_host_phy->usbphyctrl0);
 	udelay(10);
-	clrbits_le32(&phy->usbphyctrl0,
+	clrbits_le32(&exynos_usb_host_phy->usbphyctrl0,
 		     HOST_CTRL0_LINKSWRST |
 		     HOST_CTRL0_UTMISWRST);
 	udelay(20);
 
 	/* EHCI Ctrl setting */
-	setbits_le32(&phy->ehcictrl,
+	setbits_le32(&exynos_usb_host_phy->ehcictrl,
 		     EHCICTRL_ENAINCRXALIGN |
 		     EHCICTRL_ENAINCR4 |
 		     EHCICTRL_ENAINCR8 |
@@ -76,13 +73,15 @@ void setup_usb_host_phy(int hsic_gpio)
 		gpio_direction_output(hsic_gpio, 1);
 		udelay(5000);
 
-		clrbits_le32(&phy->hsicphyctrl1,
+		clrbits_le32(&exynos_usb_host_phy->hsicphyctrl1,
 			     HOST_CTRL0_SIDDQ |
 			     HOST_CTRL0_FORCESLEEP |
 			     HOST_CTRL0_FORCESUSPEND);
-		setbits_le32(&phy->hsicphyctrl1, HOST_CTRL0_PHYSWRST);
+		setbits_le32(&exynos_usb_host_phy->hsicphyctrl1,
+			     HOST_CTRL0_PHYSWRST);
 		udelay(10);
-		clrbits_le32(&phy->hsicphyctrl1, HOST_CTRL0_PHYSWRST);
+		clrbits_le32(&exynos_usb_host_phy->hsicphyctrl1,
+			     HOST_CTRL0_PHYSWRST);
 	}
 
 	/* At this point we need to wait for 50ms before talking to
diff --git a/src/cpu/samsung/exynos5250/usb.h b/src/cpu/samsung/exynos5250/usb.h
index c963436602..c951c1fbbb 100644
--- a/src/cpu/samsung/exynos5250/usb.h
+++ b/src/cpu/samsung/exynos5250/usb.h
@@ -20,6 +20,8 @@
 #ifndef CPU_SAMSUNG_EXYNOS5250_USB_H
 #define CPU_SAMSUNG_EXYNOS5250_USB_H
 
+#include "cpu.h"
+
 #define CLK_24MHZ               5
 
 #define HOST_CTRL0_PHYSWRSTALL                  (1 << 31)
@@ -57,6 +59,9 @@ struct exynos5_usb_host_phy {
         uint32_t usbotgtune;
 };
 
+static struct exynos5_usb_host_phy * const exynos_usb_host_phy =
+		(void *)EXYNOS5_USB_HOST_PHY_BASE;
+
 /* Leave hsic_gpio at 0 to not enable HSIC. */
 void setup_usb_host_phy(int hsic_gpio);
 
diff --git a/src/cpu/samsung/exynos5420/alternate_cbfs.c b/src/cpu/samsung/exynos5420/alternate_cbfs.c
index 416130305a..d19098b948 100644
--- a/src/cpu/samsung/exynos5420/alternate_cbfs.c
+++ b/src/cpu/samsung/exynos5420/alternate_cbfs.c
@@ -25,7 +25,6 @@
 #include <arch/cache.h>
 #include <console/console.h>
 #include "alternate_cbfs.h"
-#include "cpu.h"
 #include "power.h"
 #include "spi.h"
 
@@ -169,7 +168,7 @@ int init_default_cbfs_media(struct cbfs_media *media)
 	if (*iram_secondary_base == SECONDARY_BASE_BOOT_USB)
 		return initialize_exynos_usb_cbfs_media(media);
 
-	switch (samsung_get_base_power()->om_stat & OM_STAT_MASK) {
+	switch (exynos_power->om_stat & OM_STAT_MASK) {
 	case OM_STAT_SDMMC:
 		return initialize_exynos_sdmmc_cbfs_media(media);
 	case OM_STAT_SPI:
@@ -178,7 +177,7 @@ int init_default_cbfs_media(struct cbfs_media *media)
 			CONFIG_CBFS_CACHE_SIZE);
 	default:
 		printk(BIOS_EMERG, "Exynos OM_STAT value 0x%x not supported!\n",
-			samsung_get_base_power()->om_stat);
+			exynos_power->om_stat);
 		return 0;
 	}
 }
diff --git a/src/cpu/samsung/exynos5420/alternate_cbfs.h b/src/cpu/samsung/exynos5420/alternate_cbfs.h
index 3bb9c760f6..af7751d4ee 100644
--- a/src/cpu/samsung/exynos5420/alternate_cbfs.h
+++ b/src/cpu/samsung/exynos5420/alternate_cbfs.h
@@ -21,14 +21,14 @@
 #define CPU_SAMSUNG_EXYNOS5420_ALTERNATE_CBFS_H
 
 /* These are pointers to function pointers. Double indirection! */
-void * * const irom_sdmmc_read_blocks_ptr = (void * *)0x02020030;
-void * * const irom_msh_read_from_fifo_emmc_ptr = (void * *)0x02020044;
-void * * const irom_msh_end_boot_op_emmc_ptr = (void * *)0x02020048;
-void * * const irom_spi_sf_read_ptr = (void * *)0x02020058;
-void * * const irom_load_image_from_usb_ptr = (void * *)0x02020070;
+static void * * const irom_sdmmc_read_blocks_ptr = (void * *)0x02020030;
+static void * * const irom_msh_read_from_fifo_emmc_ptr = (void * *)0x02020044;
+static void * * const irom_msh_end_boot_op_emmc_ptr = (void * *)0x02020048;
+static void * * const irom_spi_sf_read_ptr = (void * *)0x02020058;
+static void * * const irom_load_image_from_usb_ptr = (void * *)0x02020070;
 
 #define SECONDARY_BASE_BOOT_USB 0xfeed0002
-u32 * const iram_secondary_base = (u32 *)0x02020018;
+static u32 * const iram_secondary_base = (u32 *)0x02020018;
 
 /* Values pulled from U-Boot, I think the manual is wrong here (for SPI) */
 #define OM_STAT_SDMMC 0x4
@@ -38,13 +38,14 @@ u32 * const iram_secondary_base = (u32 *)0x02020018;
 
 #if defined(__BOOT_BLOCK__)
 	/* A small space in IRAM to hold the romstage-only image */
-	void * const alternate_cbfs_buffer = (void *)CONFIG_CBFS_CACHE_ADDRESS;
-	size_t const alternate_cbfs_size = CONFIG_CBFS_CACHE_SIZE;
+	static void * const alternate_cbfs_buffer =
+			(void *)CONFIG_CBFS_CACHE_ADDRESS;
+	static size_t const alternate_cbfs_size = CONFIG_CBFS_CACHE_SIZE;
 #else
 	/* Just put this anywhere in RAM that's far enough from anything else */
 	/* TODO: Find a better way to "reserve" this region? */
-	void * const alternate_cbfs_buffer = (void *)0x77400000;
-	size_t const alternate_cbfs_size = 0xc00000;
+	static void * const alternate_cbfs_buffer = (void *)0x77400000;
+	static size_t const alternate_cbfs_size = 0xc00000;
 #endif
 
 #endif /* CPU_SAMSUNG_EXYNOS5420_ALTERNATE_CBFS_H */
diff --git a/src/cpu/samsung/exynos5420/clk.h b/src/cpu/samsung/exynos5420/clk.h
index 3f97319076..83d4ad6320 100644
--- a/src/cpu/samsung/exynos5420/clk.h
+++ b/src/cpu/samsung/exynos5420/clk.h
@@ -23,6 +23,8 @@
 
 #include <stdint.h>
 
+#include "cpu.h"
+
 enum periph_id;
 
 /* This master list of PLLs is ordered arbitrarily. */
@@ -56,8 +58,6 @@ unsigned long clock_get_periph_rate(enum periph_id peripheral);
 #include "pinmux.h"
 
 
-#define MCT_ADDRESS 0x101c0000
-
 #define MCT_HZ 24000000
 
 /*
@@ -597,7 +597,10 @@ struct exynos5420_clock {
 	uint32_t	cmu_kfc_version;	/* 0x1003bff0 */
 };
 
-struct exynos5_mct_regs {
+static struct exynos5420_clock * const exynos_clock =
+		(void *)EXYNOS5_CLOCK_BASE;
+
+struct exynos5_mct {
 	uint32_t	mct_cfg;
 	uint8_t		reserved0[0xfc];
 	uint32_t	g_cnt_l;
@@ -655,6 +658,9 @@ struct exynos5_mct_regs {
 	uint32_t	l1_wstat;
 };
 
+static struct exynos5_mct * const exynos_mct =
+		(void *)EXYNOS5_MULTI_CORE_TIMER_BASE;
+
 #define EXYNOS5_EPLLCON0_LOCKED_SHIFT	29  /* EPLL Locked bit position*/
 #define EPLL_SRC_CLOCK			24000000  /*24 MHz Cristal Input */
 #define TIMEOUT_EPLL_LOCK		1000
diff --git a/src/cpu/samsung/exynos5420/clock.c b/src/cpu/samsung/exynos5420/clock.c
index 8a8e58954a..f7436f22c3 100644
--- a/src/cpu/samsung/exynos5420/clock.c
+++ b/src/cpu/samsung/exynos5420/clock.c
@@ -17,13 +17,12 @@
  * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
  */
 
-#include <console/console.h>
+#include <assert.h>
 #include <stdlib.h>
 #include <timer.h>
-#include <assert.h>
 #include <arch/io.h>
+#include <console/console.h>
 #include "clk.h"
-#include "cpu.h"
 #include "periph.h"
 
 /* input clock of PLL: SMDK5420 has 24MHz input clock */
@@ -43,40 +42,39 @@ static struct st_epll_con_val epll_div[] = {
 /* exynos5: return pll clock frequency */
 unsigned long get_pll_clk(int pllreg)
 {
-	struct exynos5420_clock *clk = samsung_get_base_clock();
 	unsigned long r, m, p, s, k = 0, mask, fout;
 	unsigned int freq;
 
 	switch (pllreg) {
 	case APLL:
-		r = readl(&clk->apll_con0);
+		r = readl(&exynos_clock->apll_con0);
 		break;
 	case MPLL:
-		r = readl(&clk->mpll_con0);
+		r = readl(&exynos_clock->mpll_con0);
 		break;
 	case EPLL:
-		r = readl(&clk->epll_con0);
-		k = readl(&clk->epll_con1);
+		r = readl(&exynos_clock->epll_con0);
+		k = readl(&exynos_clock->epll_con1);
 		break;
 	case VPLL:
-		r = readl(&clk->vpll_con0);
-		k = readl(&clk->vpll_con1);
+		r = readl(&exynos_clock->vpll_con0);
+		k = readl(&exynos_clock->vpll_con1);
 		break;
 	case BPLL:
-		r = readl(&clk->bpll_con0);
+		r = readl(&exynos_clock->bpll_con0);
 		break;
 	case RPLL:
-		r = readl(&clk->rpll_con0);
-		k = readl(&clk->rpll_con1);
+		r = readl(&exynos_clock->rpll_con0);
+		k = readl(&exynos_clock->rpll_con1);
 		break;
 	case SPLL:
-		r = readl(&clk->spll_con0);
+		r = readl(&exynos_clock->spll_con0);
 		break;
 	case CPLL:
-		r = readl(&clk->cpll_con0);
+		r = readl(&exynos_clock->cpll_con0);
 		break;
 	case DPLL:
-		r = readl(&clk->dpll_con0);
+		r = readl(&exynos_clock->dpll_con0);
 		break;
 	default:
 		printk(BIOS_DEBUG, "Unsupported PLL (%d)\n", pllreg);
@@ -168,52 +166,51 @@ unsigned long clock_get_periph_rate(enum periph_id peripheral)
 {
 	unsigned long sclk;
 	unsigned int src, div;
-	struct exynos5420_clock *clk = samsung_get_base_clock();
 
 	switch (peripheral) {
 	case PERIPH_ID_UART0:
-		src = (readl(&clk->clk_src_peric0) >> 4) & 0x7;
-		div = (readl(&clk->clk_div_peric0) >> 8) & 0xf;
+		src = (readl(&exynos_clock->clk_src_peric0) >> 4) & 0x7;
+		div = (readl(&exynos_clock->clk_div_peric0) >> 8) & 0xf;
 		break;
 	case PERIPH_ID_UART1:
-		src = (readl(&clk->clk_src_peric0) >> 8) & 0x7;
-		div = (readl(&clk->clk_div_peric0) >> 12) & 0xf;
+		src = (readl(&exynos_clock->clk_src_peric0) >> 8) & 0x7;
+		div = (readl(&exynos_clock->clk_div_peric0) >> 12) & 0xf;
 		break;
 	case PERIPH_ID_UART2:
-		src = (readl(&clk->clk_src_peric0) >> 12) & 0x7;
-		div = (readl(&clk->clk_div_peric0) >> 16) & 0xf;
+		src = (readl(&exynos_clock->clk_src_peric0) >> 12) & 0x7;
+		div = (readl(&exynos_clock->clk_div_peric0) >> 16) & 0xf;
 		break;
 	case PERIPH_ID_UART3:
-		src = (readl(&clk->clk_src_peric0) >> 16) & 0x7;
-		div = (readl(&clk->clk_div_peric0) >> 20) & 0xf;
+		src = (readl(&exynos_clock->clk_src_peric0) >> 16) & 0x7;
+		div = (readl(&exynos_clock->clk_div_peric0) >> 20) & 0xf;
 		break;
 	case PERIPH_ID_PWM0:
 	case PERIPH_ID_PWM1:
 	case PERIPH_ID_PWM2:
 	case PERIPH_ID_PWM3:
 	case PERIPH_ID_PWM4:
-		src = (readl(&clk->clk_src_peric0) >> 24) & 0x7;
-		div = (readl(&clk->clk_div_peric0) >> 28) & 0x7;
+		src = (readl(&exynos_clock->clk_src_peric0) >> 24) & 0x7;
+		div = (readl(&exynos_clock->clk_div_peric0) >> 28) & 0x7;
 		break;
 	case PERIPH_ID_SPI0:
-		src = (readl(&clk->clk_src_peric1) >> 20) & 0x7;
-		div = (readl(&clk->clk_div_peric1) >> 20) & 0xf;
+		src = (readl(&exynos_clock->clk_src_peric1) >> 20) & 0x7;
+		div = (readl(&exynos_clock->clk_div_peric1) >> 20) & 0xf;
 		break;
 	case PERIPH_ID_SPI1:
-		src = (readl(&clk->clk_src_peric1) >> 24) & 0x7;
-		div = (readl(&clk->clk_div_peric1) >> 24) & 0xf;
+		src = (readl(&exynos_clock->clk_src_peric1) >> 24) & 0x7;
+		div = (readl(&exynos_clock->clk_div_peric1) >> 24) & 0xf;
 		break;
 	case PERIPH_ID_SPI2:
-		src = (readl(&clk->clk_src_peric1) >> 28) & 0x7;
-		div = (readl(&clk->clk_div_peric1) >> 28) & 0xf;
+		src = (readl(&exynos_clock->clk_src_peric1) >> 28) & 0x7;
+		div = (readl(&exynos_clock->clk_div_peric1) >> 28) & 0xf;
 		break;
 	case PERIPH_ID_SPI3:	/* aka SPI0_ISP */
-		src = (readl(&clk->clk_src_isp) >> 16) & 0x7;
-		div = (readl(&clk->clk_div_isp0) >> 0) & 0x7;
+		src = (readl(&exynos_clock->clk_src_isp) >> 16) & 0x7;
+		div = (readl(&exynos_clock->clk_div_isp0) >> 0) & 0x7;
 		break;
 	case PERIPH_ID_SPI4:	/* aka SPI1_ISP */
-		src = (readl(&clk->clk_src_isp) >> 12) & 0x7;
-		div = (readl(&clk->clk_div_isp1) >> 4) & 0x7;
+		src = (readl(&exynos_clock->clk_src_isp) >> 12) & 0x7;
+		div = (readl(&exynos_clock->clk_div_isp1) >> 4) & 0x7;
 		break;
 	case PERIPH_ID_I2C0:
 	case PERIPH_ID_I2C1:
@@ -232,7 +229,7 @@ unsigned long clock_get_periph_rate(enum periph_id peripheral)
 		 * TODO: Add a helper function like with the peripheral clock
 		 * select fields?
 		 */
-		src = (readl(&clk->clk_src_top1) >> 8) & 0x3;
+		src = (readl(&exynos_clock->clk_src_top1) >> 8) & 0x3;
 		if (src == 0x0)
 			src = CPLL;
 		else if (src == 0x1)
@@ -243,7 +240,7 @@ unsigned long clock_get_periph_rate(enum periph_id peripheral)
 			return -1;
 
 		sclk = get_pll_clk(src);
-		div = ((readl(&clk->clk_div_top1) >> 8) & 0x3f) + 1;
+		div = ((readl(&exynos_clock->clk_div_top1) >> 8) & 0x3f) + 1;
 		return sclk / div;
 	default:
 		printk(BIOS_DEBUG, "%s: invalid peripheral %d",
@@ -265,13 +262,12 @@ unsigned long clock_get_periph_rate(enum periph_id peripheral)
 /* exynos5: return ARM clock frequency */
 unsigned long get_arm_clk(void)
 {
-	struct exynos5420_clock *clk = samsung_get_base_clock();
 	unsigned long div;
 	unsigned long armclk;
 	unsigned int arm_ratio;
 	unsigned int arm2_ratio;
 
-	div = readl(&clk->clk_div_cpu0);
+	div = readl(&exynos_clock->clk_div_cpu0);
 
 	/* ARM_RATIO: [2:0], ARM2_RATIO: [30:28] */
 	arm_ratio = (div >> 0) & 0x7;
@@ -286,12 +282,11 @@ unsigned long get_arm_clk(void)
 /* exynos5: get the mmc clock */
 static unsigned long get_mmc_clk(int dev_index)
 {
-	struct exynos5420_clock *clk = samsung_get_base_clock();
 	unsigned long uclk, sclk;
 	unsigned int sel, ratio;
 	int shift = 0;
 
-	sel = readl(&clk->clk_src_fsys);
+	sel = readl(&exynos_clock->clk_src_fsys);
 	sel = (sel >> ((dev_index * 4) + 8)) & 0x7;
 
 	if (sel == 0x3)
@@ -301,7 +296,7 @@ static unsigned long get_mmc_clk(int dev_index)
 	else
 		return 0;
 
-	ratio = readl(&clk->clk_div_fsys1);
+	ratio = readl(&exynos_clock->clk_div_fsys1);
 
 	shift = dev_index * 10;
 
@@ -315,11 +310,10 @@ static unsigned long get_mmc_clk(int dev_index)
 /* exynos5: set the mmc clock */
 void set_mmc_clk(int dev_index, unsigned int div)
 {
-	struct exynos5420_clock *clk = samsung_get_base_clock();
 	void *addr;
 	unsigned int val, shift;
 
-	addr = &clk->clk_div_fsys1;
+	addr = &exynos_clock->clk_div_fsys1;
 	shift = dev_index * 10;
 
 	val = readl(addr);
@@ -361,7 +355,6 @@ int clock_set_dwmci(enum periph_id peripheral)
 
 void clock_ll_set_pre_ratio(enum periph_id periph_id, unsigned divisor)
 {
-	struct exynos5420_clock *clk = samsung_get_base_clock();
 	unsigned shift;
 	unsigned mask = 0xff;
 	u32 *reg;
@@ -376,23 +369,23 @@ void clock_ll_set_pre_ratio(enum periph_id periph_id, unsigned divisor)
 	 */
 	switch (periph_id) {
 	case PERIPH_ID_SPI0:
-		reg = &clk->clk_div_peric4;
+		reg = &exynos_clock->clk_div_peric4;
 		shift = 8;
 		break;
 	case PERIPH_ID_SPI1:
-		reg = &clk->clk_div_peric4;
+		reg = &exynos_clock->clk_div_peric4;
 		shift = 16;
 		break;
 	case PERIPH_ID_SPI2:
-		reg = &clk->clk_div_peric4;
+		reg = &exynos_clock->clk_div_peric4;
 		shift = 24;
 		break;
 	case PERIPH_ID_SPI3:
-		reg = &clk->clk_div_isp1;
+		reg = &exynos_clock->clk_div_isp1;
 		shift = 0;
 		break;
 	case PERIPH_ID_SPI4:
-		reg = &clk->clk_div_isp1;
+		reg = &exynos_clock->clk_div_isp1;
 		shift = 8;
 		break;
 	default:
@@ -405,30 +398,29 @@ void clock_ll_set_pre_ratio(enum periph_id periph_id, unsigned divisor)
 
 void clock_ll_set_ratio(enum periph_id periph_id, unsigned divisor)
 {
-	struct exynos5420_clock *clk = samsung_get_base_clock();
 	unsigned shift;
 	unsigned mask = 0xf;
 	u32 *reg;
 
 	switch (periph_id) {
 	case PERIPH_ID_SPI0:
-		reg = &clk->clk_div_peric1;
+		reg = &exynos_clock->clk_div_peric1;
 		shift = 20;
 		break;
 	case PERIPH_ID_SPI1:
-		reg = &clk->clk_div_peric1;
+		reg = &exynos_clock->clk_div_peric1;
 		shift = 24;
 		break;
 	case PERIPH_ID_SPI2:
-		reg = &clk->clk_div_peric1;
+		reg = &exynos_clock->clk_div_peric1;
 		shift = 28;
 		break;
 	case PERIPH_ID_SPI3:
-		reg = &clk->clk_div_isp1;
+		reg = &exynos_clock->clk_div_isp1;
 		shift = 16;
 		break;
 	case PERIPH_ID_SPI4:
-		reg = &clk->clk_div_isp1;
+		reg = &exynos_clock->clk_div_isp1;
 		shift = 20;
 		break;
 	default:
@@ -529,7 +521,6 @@ int clock_set_rate(enum periph_id periph_id, unsigned int rate)
 
 int clock_set_mshci(enum periph_id peripheral)
 {
-	struct exynos5420_clock *clk = samsung_get_base_clock();
 	u32 *addr;
 	unsigned int clock;
 	unsigned int tmp;
@@ -546,10 +537,10 @@ int clock_set_mshci(enum periph_id peripheral)
 	 */
 	switch (peripheral) {
 	case PERIPH_ID_SDMMC0:
-		addr = &clk->clk_div_fsys1;
+		addr = &exynos_clock->clk_div_fsys1;
 		break;
 	case PERIPH_ID_SDMMC2:
-		addr = &clk->clk_div_fsys2;
+		addr = &exynos_clock->clk_div_fsys2;
 		break;
 	default:
 		printk(BIOS_DEBUG, "invalid peripheral\n");
@@ -571,9 +562,8 @@ int clock_epll_set_rate(unsigned long rate)
 	unsigned int i;
 	unsigned int lockcnt;
 	struct mono_time current, end;
-	struct exynos5420_clock *clk = samsung_get_base_clock();
 
-	epll_con = readl(&clk->epll_con0);
+	epll_con = readl(&exynos_clock->epll_con0);
 	epll_con &= ~((EPLL_CON0_LOCK_DET_EN_MASK <<
 			EPLL_CON0_LOCK_DET_EN_SHIFT) |
 		EPLL_CON0_MDIV_MASK << EPLL_CON0_MDIV_SHIFT |
@@ -601,15 +591,15 @@ int clock_epll_set_rate(unsigned long rate)
 	 */
 	lockcnt = 3000 * epll_div[i].p_div;
 
-	writel(lockcnt, &clk->epll_lock);
-	writel(epll_con, &clk->epll_con0);
-	writel(epll_con_k, &clk->epll_con1);
+	writel(lockcnt, &exynos_clock->epll_lock);
+	writel(epll_con, &exynos_clock->epll_con0);
+	writel(epll_con_k, &exynos_clock->epll_con1);
 
 	timer_monotonic_get(&current);
 	end = current;
 	mono_time_add_msecs(&end, TIMEOUT_EPLL_LOCK);
 
-	while (!(readl(&clk->epll_con0) &
+	while (!(readl(&exynos_clock->epll_con0) &
 			(0x1 << EXYNOS5_EPLLCON0_LOCKED_SHIFT))) {
 		if (mono_time_after(&current, &end)) {
 			printk(BIOS_DEBUG, "%s: Timeout waiting for EPLL lock\n", __func__);
@@ -623,15 +613,12 @@ int clock_epll_set_rate(unsigned long rate)
 
 void clock_select_i2s_clk_source(void)
 {
-	struct exynos5420_clock *clk = samsung_get_base_clock();
-
-	clrsetbits_le32(&clk->clk_src_peric1, AUDIO1_SEL_MASK,
+	clrsetbits_le32(&exynos_clock->clk_src_peric1, AUDIO1_SEL_MASK,
 			(CLK_SRC_SCLK_EPLL));
 }
 
 int clock_set_i2s_clk_prescaler(unsigned int src_frq, unsigned int dst_frq)
 {
-	struct exynos5420_clock *clk = samsung_get_base_clock();
 	unsigned int div ;
 
 	if ((dst_frq == 0) || (src_frq == 0)) {
@@ -646,7 +633,7 @@ int clock_set_i2s_clk_prescaler(unsigned int src_frq, unsigned int dst_frq)
 		printk(BIOS_DEBUG, "src frq = %d des frq = %d ", src_frq, dst_frq);
 		return -1;
 	}
-	clrsetbits_le32(&clk->clk_div_peric4, AUDIO_1_RATIO_MASK,
+	clrsetbits_le32(&exynos_clock->clk_div_peric4, AUDIO_1_RATIO_MASK,
 				(div & AUDIO_1_RATIO_MASK));
 	return 0;
 }
diff --git a/src/cpu/samsung/exynos5420/clock_init.c b/src/cpu/samsung/exynos5420/clock_init.c
index 15cd0c0368..cfac01e307 100644
--- a/src/cpu/samsung/exynos5420/clock_init.c
+++ b/src/cpu/samsung/exynos5420/clock_init.c
@@ -19,8 +19,8 @@
 
 /* Clock setup for SMDK5420 board based on EXYNOS5 */
 
-#include <console/console.h>
 #include <delay.h>
+#include <console/console.h>
 #include "clk.h"
 #include "cpu.h"
 #include "dp.h"
@@ -29,196 +29,192 @@
 
 void system_clock_init(void)
 {
-	struct exynos5420_clock *clk =
-		(struct exynos5420_clock *)EXYNOS5420_CLOCK_BASE;
-	struct exynos5_mct_regs *mct_regs =
-		(struct exynos5_mct_regs *)EXYNOS5_MULTI_CORE_TIMER_BASE;
 	u32 val;
 
 	/* Turn on the MCT as early as possible. */
-	mct_regs->g_tcon |= (1 << 8);
+	exynos_mct->g_tcon |= (1 << 8);
 
 	/* PLL locktime */
-	writel(APLL_LOCK_VAL, &clk->apll_lock);
-	writel(MPLL_LOCK_VAL, &clk->mpll_lock);
-	writel(BPLL_LOCK_VAL, &clk->bpll_lock);
-	writel(CPLL_LOCK_VAL, &clk->cpll_lock);
-	writel(DPLL_LOCK_VAL, &clk->dpll_lock);
-	writel(EPLL_LOCK_VAL, &clk->epll_lock);
-	writel(VPLL_LOCK_VAL, &clk->vpll_lock);
-	writel(IPLL_LOCK_VAL, &clk->ipll_lock);
-	writel(SPLL_LOCK_VAL, &clk->spll_lock);
-	writel(KPLL_LOCK_VAL, &clk->kpll_lock);
-        writel(RPLL_LOCK_VAL, &clk->rpll_lock);
-
-	setbits_le32(&clk->clk_src_cpu, MUX_HPM_SEL_MASK);
-
-	writel(0, &clk->clk_src_top6);
-
-	writel(0, &clk->clk_src_cdrex);
-	writel(SRC_KFC_HPM_SEL, &clk->clk_src_kfc);
-	writel(HPM_RATIO,  &clk->clk_div_cpu1);
-	writel(CLK_DIV_CPU0_VAL, &clk->clk_div_cpu0);
+	writel(APLL_LOCK_VAL, &exynos_clock->apll_lock);
+	writel(MPLL_LOCK_VAL, &exynos_clock->mpll_lock);
+	writel(BPLL_LOCK_VAL, &exynos_clock->bpll_lock);
+	writel(CPLL_LOCK_VAL, &exynos_clock->cpll_lock);
+	writel(DPLL_LOCK_VAL, &exynos_clock->dpll_lock);
+	writel(EPLL_LOCK_VAL, &exynos_clock->epll_lock);
+	writel(VPLL_LOCK_VAL, &exynos_clock->vpll_lock);
+	writel(IPLL_LOCK_VAL, &exynos_clock->ipll_lock);
+	writel(SPLL_LOCK_VAL, &exynos_clock->spll_lock);
+	writel(KPLL_LOCK_VAL, &exynos_clock->kpll_lock);
+        writel(RPLL_LOCK_VAL, &exynos_clock->rpll_lock);
+
+	setbits_le32(&exynos_clock->clk_src_cpu, MUX_HPM_SEL_MASK);
+
+	writel(0, &exynos_clock->clk_src_top6);
+
+	writel(0, &exynos_clock->clk_src_cdrex);
+	writel(SRC_KFC_HPM_SEL, &exynos_clock->clk_src_kfc);
+	writel(HPM_RATIO,  &exynos_clock->clk_div_cpu1);
+	writel(CLK_DIV_CPU0_VAL, &exynos_clock->clk_div_cpu0);
 
 	/* switch A15 clock source to OSC clock before changing APLL */
-	clrbits_le32(&clk->clk_src_cpu, APLL_FOUT);
+	clrbits_le32(&exynos_clock->clk_src_cpu, APLL_FOUT);
 
 	/* Set APLL */
-	writel(APLL_CON1_VAL, &clk->apll_con1);
+	writel(APLL_CON1_VAL, &exynos_clock->apll_con1);
 	val = set_pll(225, 3, 0);	/* FOUT=1800MHz */
-	writel(val, &clk->apll_con0);
-	while ((readl(&clk->apll_con0) & PLL_LOCKED) == 0)
+	writel(val, &exynos_clock->apll_con0);
+	while ((readl(&exynos_clock->apll_con0) & PLL_LOCKED) == 0)
 		;
 
 	/* now it is safe to switch to APLL */
-	setbits_le32(&clk->clk_src_cpu, APLL_FOUT);
+	setbits_le32(&exynos_clock->clk_src_cpu, APLL_FOUT);
 
-	writel(SRC_KFC_HPM_SEL, &clk->clk_src_kfc);
-	writel(CLK_DIV_KFC_VAL, &clk->clk_div_kfc0);
+	writel(SRC_KFC_HPM_SEL, &exynos_clock->clk_src_kfc);
+	writel(CLK_DIV_KFC_VAL, &exynos_clock->clk_div_kfc0);
 
 	/* switch A7 clock source to OSC clock before changing KPLL */
-	clrbits_le32(&clk->clk_src_kfc, KPLL_FOUT);
+	clrbits_le32(&exynos_clock->clk_src_kfc, KPLL_FOUT);
 
 	/* Set KPLL*/
-	writel(KPLL_CON1_VAL, &clk->kpll_con1);
+	writel(KPLL_CON1_VAL, &exynos_clock->kpll_con1);
 	val = set_pll(0x190, 0x4, 0x2);
-	writel(val, &clk->kpll_con0);
-	while ((readl(&clk->kpll_con0) & PLL_LOCKED) == 0)
+	writel(val, &exynos_clock->kpll_con0);
+	while ((readl(&exynos_clock->kpll_con0) & PLL_LOCKED) == 0)
 		;
 
 	/* now it is safe to switch to KPLL */
-	setbits_le32(&clk->clk_src_kfc, KPLL_FOUT);
+	setbits_le32(&exynos_clock->clk_src_kfc, KPLL_FOUT);
 
 	/* Set MPLL */
-	writel(MPLL_CON1_VAL, &clk->mpll_con1);
+	writel(MPLL_CON1_VAL, &exynos_clock->mpll_con1);
 	val = set_pll(0xc8, 0x3, 0x1);
-	writel(val, &clk->mpll_con0);
-	while ((readl(&clk->mpll_con0) & PLL_LOCKED) == 0)
+	writel(val, &exynos_clock->mpll_con0);
+	while ((readl(&exynos_clock->mpll_con0) & PLL_LOCKED) == 0)
 		;
 
 	/* Set DPLL */
-	writel(DPLL_CON1_VAL, &clk->dpll_con1);
+	writel(DPLL_CON1_VAL, &exynos_clock->dpll_con1);
 	val = set_pll(0x190, 0x4, 0x2);
-	writel(val, &clk->dpll_con0);
-	while ((readl(&clk->dpll_con0) & PLL_LOCKED) == 0)
+	writel(val, &exynos_clock->dpll_con0);
+	while ((readl(&exynos_clock->dpll_con0) & PLL_LOCKED) == 0)
 		;
 
 	/* Set EPLL */
-	writel(EPLL_CON2_VAL, &clk->epll_con2);
-	writel(EPLL_CON1_VAL, &clk->epll_con1);
+	writel(EPLL_CON2_VAL, &exynos_clock->epll_con2);
+	writel(EPLL_CON1_VAL, &exynos_clock->epll_con1);
 	val = set_pll(0x64, 0x2, 0x1);
-	writel(val, &clk->epll_con0);
-	while ((readl(&clk->epll_con0) & PLL_LOCKED) == 0)
+	writel(val, &exynos_clock->epll_con0);
+	while ((readl(&exynos_clock->epll_con0) & PLL_LOCKED) == 0)
 		;
 
 	/* Set CPLL */
-	writel(CPLL_CON1_VAL, &clk->cpll_con1);
+	writel(CPLL_CON1_VAL, &exynos_clock->cpll_con1);
 	val = set_pll(0xde, 0x4, 0x1);
-	writel(val, &clk->cpll_con0);
-	while ((readl(&clk->cpll_con0) & PLL_LOCKED) == 0)
+	writel(val, &exynos_clock->cpll_con0);
+	while ((readl(&exynos_clock->cpll_con0) & PLL_LOCKED) == 0)
 		;
 
 	/* Set IPLL */
-	writel(IPLL_CON1_VAL, &clk->ipll_con1);
+	writel(IPLL_CON1_VAL, &exynos_clock->ipll_con1);
 	val = set_pll(0xB9, 0x3, 0x2);
-	writel(val, &clk->ipll_con0);
-	while ((readl(&clk->ipll_con0) & PLL_LOCKED) == 0)
+	writel(val, &exynos_clock->ipll_con0);
+	while ((readl(&exynos_clock->ipll_con0) & PLL_LOCKED) == 0)
 		;
 
 	/* Set VPLL */
-	writel(VPLL_CON1_VAL, &clk->vpll_con1);
+	writel(VPLL_CON1_VAL, &exynos_clock->vpll_con1);
 	val = set_pll(0xd7, 0x3, 0x2);
-	writel(val, &clk->vpll_con0);
-	while ((readl(&clk->vpll_con0) & PLL_LOCKED) == 0)
+	writel(val, &exynos_clock->vpll_con0);
+	while ((readl(&exynos_clock->vpll_con0) & PLL_LOCKED) == 0)
 		;
 
 	/* Set BPLL */
-	writel(BPLL_CON1_VAL, &clk->bpll_con1);
+	writel(BPLL_CON1_VAL, &exynos_clock->bpll_con1);
 	val = set_pll(0xc8, 0x3, 0x1);
-	writel(val, &clk->bpll_con0);
-	while ((readl(&clk->bpll_con0) & PLL_LOCKED) == 0)
+	writel(val, &exynos_clock->bpll_con0);
+	while ((readl(&exynos_clock->bpll_con0) & PLL_LOCKED) == 0)
 		;
 
 	/* Set SPLL */
-	writel(SPLL_CON1_VAL, &clk->spll_con1);
+	writel(SPLL_CON1_VAL, &exynos_clock->spll_con1);
 	val = set_pll(200, 0x3, 0x2);	/* 400MHz */
-	writel(val, &clk->spll_con0);
-	while ((readl(&clk->spll_con0) & PLL_LOCKED) == 0)
+	writel(val, &exynos_clock->spll_con0);
+	while ((readl(&exynos_clock->spll_con0) & PLL_LOCKED) == 0)
 		;
 
         /* We use RPLL as the source for FIMD video stream clock */
-	writel(RPLL_CON1_VAL, &clk->rpll_con1);
-	writel(RPLL_CON2_VAL, &clk->rpll_con2);
+	writel(RPLL_CON1_VAL, &exynos_clock->rpll_con1);
+	writel(RPLL_CON2_VAL, &exynos_clock->rpll_con2);
 	/* computed by gabe from first principles; u-boot is probably
 	 * wrong again
 	 */
 	val = set_pll(0xa0, 0x3, 0x2);
-	writel(val, &clk->rpll_con0);
+	writel(val, &exynos_clock->rpll_con0);
 	/* note: this is a meaningless exercise. The hardware lock
 	 * detection does not work. So this just spins for some
 	 * time and is done. NO indication of success should attach
 	 * to this or any other spin on a con0 value.
 	 */
-	while ((readl(&clk->rpll_con0) & PLL_LOCKED) == 0)
+	while ((readl(&exynos_clock->rpll_con0) & PLL_LOCKED) == 0)
 		;
 
-	writel(CLK_DIV_CDREX0_VAL, &clk->clk_div_cdrex0);
-	writel(CLK_DIV_CDREX1_VAL, &clk->clk_div_cdrex1);
+	writel(CLK_DIV_CDREX0_VAL, &exynos_clock->clk_div_cdrex0);
+	writel(CLK_DIV_CDREX1_VAL, &exynos_clock->clk_div_cdrex1);
 
-	writel(CLK_SRC_TOP0_VAL, &clk->clk_src_top0);
-	writel(CLK_SRC_TOP1_VAL, &clk->clk_src_top1);
-	writel(CLK_SRC_TOP2_VAL, &clk->clk_src_top2);
-	writel(CLK_SRC_TOP7_VAL, &clk->clk_src_top7);
+	writel(CLK_SRC_TOP0_VAL, &exynos_clock->clk_src_top0);
+	writel(CLK_SRC_TOP1_VAL, &exynos_clock->clk_src_top1);
+	writel(CLK_SRC_TOP2_VAL, &exynos_clock->clk_src_top2);
+	writel(CLK_SRC_TOP7_VAL, &exynos_clock->clk_src_top7);
 
-	writel(CLK_DIV_TOP0_VAL, &clk->clk_div_top0);
-	writel(CLK_DIV_TOP1_VAL, &clk->clk_div_top1);
-	writel(CLK_DIV_TOP2_VAL, &clk->clk_div_top2);
+	writel(CLK_DIV_TOP0_VAL, &exynos_clock->clk_div_top0);
+	writel(CLK_DIV_TOP1_VAL, &exynos_clock->clk_div_top1);
+	writel(CLK_DIV_TOP2_VAL, &exynos_clock->clk_div_top2);
 
-	writel(0, &clk->clk_src_top10);
-	writel(0, &clk->clk_src_top11);
-	writel(0, &clk->clk_src_top12);
+	writel(0, &exynos_clock->clk_src_top10);
+	writel(0, &exynos_clock->clk_src_top11);
+	writel(0, &exynos_clock->clk_src_top12);
 
-	writel(CLK_SRC_TOP3_VAL, &clk->clk_src_top3);
-	writel(CLK_SRC_TOP4_VAL, &clk->clk_src_top4);
-	writel(CLK_SRC_TOP5_VAL, &clk->clk_src_top5);
+	writel(CLK_SRC_TOP3_VAL, &exynos_clock->clk_src_top3);
+	writel(CLK_SRC_TOP4_VAL, &exynos_clock->clk_src_top4);
+	writel(CLK_SRC_TOP5_VAL, &exynos_clock->clk_src_top5);
 
 	/* DISP1 BLK CLK SELECTION */
-	writel(CLK_SRC_DISP1_0_VAL, &clk->clk_src_disp10);
-	writel(CLK_DIV_DISP1_0_VAL, &clk->clk_div_disp10);
+	writel(CLK_SRC_DISP1_0_VAL, &exynos_clock->clk_src_disp10);
+	writel(CLK_DIV_DISP1_0_VAL, &exynos_clock->clk_div_disp10);
 
 	/* AUDIO BLK */
-	writel(AUDIO0_SEL_EPLL, &clk->clk_src_mau);
-	writel(DIV_MAU_VAL, &clk->clk_div_mau);
+	writel(AUDIO0_SEL_EPLL, &exynos_clock->clk_src_mau);
+	writel(DIV_MAU_VAL, &exynos_clock->clk_div_mau);
 
 	/* FSYS */
-	writel(CLK_SRC_FSYS0_VAL, &clk->clk_src_fsys);
-	writel(CLK_DIV_FSYS0_VAL, &clk->clk_div_fsys0);
-	writel(CLK_DIV_FSYS1_VAL, &clk->clk_div_fsys1);
-	writel(CLK_DIV_FSYS2_VAL, &clk->clk_div_fsys2);
-
-	writel(CLK_SRC_ISP_VAL, &clk->clk_src_isp);
-	writel(CLK_DIV_ISP0_VAL, &clk->clk_div_isp0);
-	writel(CLK_DIV_ISP1_VAL, &clk->clk_div_isp1);
-
-	writel(CLK_SRC_PERIC0_VAL, &clk->clk_src_peric0);
-	writel(CLK_SRC_PERIC1_VAL, &clk->clk_src_peric1);
-
-	writel(CLK_DIV_PERIC0_VAL, &clk->clk_div_peric0);
-	writel(CLK_DIV_PERIC1_VAL, &clk->clk_div_peric1);
-	writel(CLK_DIV_PERIC2_VAL, &clk->clk_div_peric2);
-	writel(CLK_DIV_PERIC3_VAL, &clk->clk_div_peric3);
-	writel(CLK_DIV_PERIC4_VAL, &clk->clk_div_peric4);
-
-	writel(CLK_DIV_CPERI1_VAL, &clk->clk_div_cperi1);
-
-	writel(CLK_DIV2_RATIO, &clk->clkdiv2_ratio);
-	writel(CLK_DIV4_RATIO, &clk->clkdiv4_ratio);
-	writel(CLK_DIV_G2D, &clk->clk_div_g2d);
-
-	writel(CLK_SRC_CPU_VAL, &clk->clk_src_cpu);
-	writel(CLK_SRC_TOP6_VAL, &clk->clk_src_top6);
-	writel(CLK_SRC_CDREX_VAL, &clk->clk_src_cdrex);
-	writel(CLK_SRC_KFC_VAL, &clk->clk_src_kfc);
+	writel(CLK_SRC_FSYS0_VAL, &exynos_clock->clk_src_fsys);
+	writel(CLK_DIV_FSYS0_VAL, &exynos_clock->clk_div_fsys0);
+	writel(CLK_DIV_FSYS1_VAL, &exynos_clock->clk_div_fsys1);
+	writel(CLK_DIV_FSYS2_VAL, &exynos_clock->clk_div_fsys2);
+
+	writel(CLK_SRC_ISP_VAL, &exynos_clock->clk_src_isp);
+	writel(CLK_DIV_ISP0_VAL, &exynos_clock->clk_div_isp0);
+	writel(CLK_DIV_ISP1_VAL, &exynos_clock->clk_div_isp1);
+
+	writel(CLK_SRC_PERIC0_VAL, &exynos_clock->clk_src_peric0);
+	writel(CLK_SRC_PERIC1_VAL, &exynos_clock->clk_src_peric1);
+
+	writel(CLK_DIV_PERIC0_VAL, &exynos_clock->clk_div_peric0);
+	writel(CLK_DIV_PERIC1_VAL, &exynos_clock->clk_div_peric1);
+	writel(CLK_DIV_PERIC2_VAL, &exynos_clock->clk_div_peric2);
+	writel(CLK_DIV_PERIC3_VAL, &exynos_clock->clk_div_peric3);
+	writel(CLK_DIV_PERIC4_VAL, &exynos_clock->clk_div_peric4);
+
+	writel(CLK_DIV_CPERI1_VAL, &exynos_clock->clk_div_cperi1);
+
+	writel(CLK_DIV2_RATIO, &exynos_clock->clkdiv2_ratio);
+	writel(CLK_DIV4_RATIO, &exynos_clock->clkdiv4_ratio);
+	writel(CLK_DIV_G2D, &exynos_clock->clk_div_g2d);
+
+	writel(CLK_SRC_CPU_VAL, &exynos_clock->clk_src_cpu);
+	writel(CLK_SRC_TOP6_VAL, &exynos_clock->clk_src_top6);
+	writel(CLK_SRC_CDREX_VAL, &exynos_clock->clk_src_cdrex);
+	writel(CLK_SRC_KFC_VAL, &exynos_clock->clk_src_kfc);
 }
 
 void clock_gate(void)
diff --git a/src/cpu/samsung/exynos5420/cpu.c b/src/cpu/samsung/exynos5420/cpu.c
index f3d5282b6b..a0c33ca378 100644
--- a/src/cpu/samsung/exynos5420/cpu.c
+++ b/src/cpu/samsung/exynos5420/cpu.c
@@ -59,7 +59,7 @@ static void tzpc_init(void)
 
 static void set_cpu_id(void)
 {
-	u32 pro_id = (read32((void *)EXYNOS_PRO_ID) & 0x00FFF000) >> 12;
+	u32 pro_id = (read32((void *)EXYNOS5_PRO_ID) & 0x00FFF000) >> 12;
 
 	switch (pro_id) {
 	case 0x200:
diff --git a/src/cpu/samsung/exynos5420/cpu.h b/src/cpu/samsung/exynos5420/cpu.h
index 472b6aa256..ffc83f88e4 100644
--- a/src/cpu/samsung/exynos5420/cpu.h
+++ b/src/cpu/samsung/exynos5420/cpu.h
@@ -22,16 +22,11 @@
 
 #include <arch/io.h>
 
-#define DEVICE_NOT_AVAILABLE		0
-
-#define EXYNOS_PRO_ID			0x10000000
-
-/* EXYNOS5 */
-#define EXYNOS5_GPIO_PART6_BASE		0x03860000	/* Z<6:0> */
+/* Base address registers */
+#define EXYNOS5420_GPIO_PART6_BASE	0x03860000 /* Z0 */
 #define EXYNOS5_PRO_ID			0x10000000
 #define EXYNOS5_CLOCK_BASE		0x10010000
 #define EXYNOS5_POWER_BASE		0x10040000
-#define EXYNOS5_SWRESET			0x10040400
 #define EXYNOS5_SYSREG_BASE		0x10050000
 #define EXYNOS5_TZPC1_DECPROT1SET	0x10110810
 #define EXYNOS5_MULTI_CORE_TIMER_BASE	0x101C0000
@@ -39,37 +34,39 @@
 #define EXYNOS5_ACE_SFR_BASE            0x10830000
 #define EXYNOS5_DMC_PHY0_BASE		0x10C00000
 #define EXYNOS5_DMC_PHY1_BASE		0x10C10000
-#define EXYNOS5_DMC_CTRL_BASE		0x10DD0000
+#define EXYNOS5420_DMC_DREXI_0		0x10C20000
+#define EXYNOS5420_DMC_DREXI_1		0x10C30000
+#define EXYNOS5420_DMC_TZASC_0		0x10D40000
+#define EXYNOS5420_DMC_TZASC_1		0x10D50000
+#define EXYNOS5420_USB_DRD0_XHCI_BASE	0x12000000
+#define EXYNOS5420_USB_DRD0_PHY_BASE	0x12100000
 #define EXYNOS5_USB_HOST_EHCI_BASE	0x12110000
-#define EXYNOS5_USBPHY_BASE		0x12130000
-#define EXYNOS5_USBOTG_BASE		0x12140000
-
+#define EXYNOS5_USB_HOST_PHY_BASE	0x12130000
 #define EXYNOS5_MMC_BASE		0x12200000
 #define EXYNOS5_MSHC_BASE		0x12240000
-
 #define EXYNOS5_SROMC_BASE		0x12250000
-#define EXYNOS5_UART_BASE		0x12C00000
-
+#define EXYNOS5420_USB_DRD1_XHCI_BASE	0x12400000
+#define EXYNOS5420_USB_DRD1_PHY_BASE	0x12500000
+#define EXYNOS5_UART0_BASE		0x12C00000
+#define EXYNOS5_UART1_BASE		0x12C10000
+#define EXYNOS5_UART2_BASE		0x12C20000
+#define EXYNOS5_UART3_BASE		0x12C30000
+#define EXYNOS5_I2C_BASE		0x12C60000
 #define EXYNOS5_SPI0_BASE		0x12D20000
 #define EXYNOS5_SPI1_BASE		0x12D30000
 #define EXYNOS5_SPI2_BASE		0x12D40000
-#define EXYNOS5_I2C_BASE		0x12C60000
-#define EXYNOS5_SPI_ISP_BASE		0x131A0000
 #define EXYNOS5_I2S_BASE		0x12D60000
-#define EXYNOS5_GPIO_PART3_BASE		0x13410000	/* C00..Y67 */
-#define EXYNOS5_GPIO_PART1_BASE		0x13400000	/* Y70..Y77 */
-#define EXYNOS5_GPIO_PART2_BASE		0x13400c00	/* X00..X37 */
-#define EXYNOS5_GPIO_PART4_BASE		0x14000000	/* E00..J47 */
-#define EXYNOS5_GPIO_PART5_BASE		0x14010000	/* A00..H07 */
-#define EXYNOS5_FIMD_BASE		0x14400000
-#define EXYNOS5_DISP1_CTRL_BASE		0x14420000
-#define EXYNOS5_MIPI_DSI1_BASE		0x14500000
-
-#define EXYNOS5_ADC_BASE		DEVICE_NOT_AVAILABLE
-#define EXYNOS5_MODEM_BASE		DEVICE_NOT_AVAILABLE
-
-/* Compatibility defines */
-#define EXYNOS_POWER_BASE		EXYNOS5_POWER_BASE
+#define EXYNOS5420_I2C_8910_BASE	0x12E00000
+#define EXYNOS5_UART_ISP_BASE		0x13190000
+#define EXYNOS5_SPI_ISP_BASE		0x131A0000
+#define EXYNOS5420_GPIO_PART1_BASE	0x13400000 /* Y0 */
+#define EXYNOS5420_GPIO_PART2_BASE	0x13400C00 /* X0..3 */
+#define EXYNOS5420_GPIO_PART3_BASE	0x13410000 /* C0..4, D1, Y0..6 */
+#define EXYNOS5420_GPIO_PART4_BASE	0x14000000 /* E0..1, F0..1, G0..2, J4 */
+#define EXYNOS5420_GPIO_PART5_BASE	0x14010000 /* A0..2, B0..4, H0 */
+#define EXYNOS5420_MIPI_DSIM_BASE	0x14500000
+#define EXYNOS5_DP0_BASE		0x14510000
+#define EXYNOS5_DP1_BASE		0x145B0000
 
 /* Marker values stored at the bottom of IRAM stack by SPL */
 #define EXYNOS5_SPL_MARKER	0xb004f1a9	/* hexspeak word: bootflag */
@@ -102,111 +99,8 @@
  */
 #define DECPROTXSET		0xFF
 
-/* EXYNOS5420 Common*/
-#define EXYNOS5420_I2C_SPACING		0x10000
-
-#define EXYNOS5420_GPIO_PART6_BASE	0x03860000
-#define EXYNOS5420_PRO_ID		0x10000000
-#define EXYNOS5420_CLOCK_BASE		0x10010000
-#define EXYNOS5420_POWER_BASE		0x10040000
-#define EXYNOS5420_SWRESET		0x10040400
-#define EXYNOS5420_SYSREG_BASE		0x10050000
-#define EXYNOS5420_WATCHDOG_BASE	0x101D0000
-#define EXYNOS5420_DMC_PHY0_BASE	0x10C00000
-#define EXYNOS5420_DMC_PHY1_BASE	0x10C10000
-#define EXYNOS5420_DMC_DREXI_0		0x10C20000
-#define EXYNOS5420_DMC_DREXI_1		0x10C30000
-#define EXYNOS5420_DMC_TZASC_0		0x10D40000
-#define EXYNOS5420_DMC_TZASC_1		0x10D50000
-#define EXYNOS5420_USB_DRD0_XHCI_BASE	0x12000000
-#define EXYNOS5420_USB_DRD0_PHY_BASE	0x12100000
-#define EXYNOS5420_USB_HOST_EHCI_BASE	0x12110000
-#define EXYNOS5420_USB_HOST_PHY_BASE	0x12130000
-#define EXYNOS5420_MMC_BASE		0x12200000
-#define EXYNOS5420_SROMC_BASE		0x12250000
-#define EXYNOS5420_USB_DRD1_XHCI_BASE	0x12400000
-#define EXYNOS5420_USB_DRD1_PHY_BASE	0x12500000
-#define EXYNOS5420_UART_BASE		0x12C00000
-#define EXYNOS5420_I2C_BASE		0x12C60000
-#define EXYNOS5420_I2C_8910_BASE	0x12E00000
-#define EXYNOS5420_SPI_BASE		0x12D20000
-#define EXYNOS5420_I2S_BASE		0x12D60000
-#define EXYNOS5420_SPI_ISP_BASE		0x131A0000
-#define EXYNOS5420_GPIO_PART2_BASE	0x13400000
-#define EXYNOS5420_GPIO_PART3_BASE	0x13400C00
-#define EXYNOS5420_GPIO_PART4_BASE	0x13410000
-#define EXYNOS5420_GPIO_PART5_BASE	0x14000000
-#define EXYNOS5420_GPIO_PART1_BASE	0x14010000
-#define EXYNOS5420_MIPI_DSIM_BASE	0x14500000
-#define EXYNOS5420_DP_BASE		0x145B0000
-#define EXYNOS5420_INF_REG_BASE		0x10040800
-
-
-#define EXYNOS5420_FIMD_BASE		DEVICE_NOT_AVAILABLE
-#define EXYNOS5420_ADC_BASE		DEVICE_NOT_AVAILABLE
-#define EXYNOS5420_MODEM_BASE		DEVICE_NOT_AVAILABLE
-
-#define ARM_CORE0_CONFIG		(EXYNOS5420_POWER_BASE + 0x2000)
-#define ARM_CORE0_STATUS		(EXYNOS5420_POWER_BASE + 0x2004)
-#define CORE_CONFIG_OFFSET		0x80
-#define CORE_COUNT			0x8
-
-/*
- * POWER
- */
-#define PMU_BASE			EXYNOS5420_POWER_BASE
-#define SW_RST_REG_OFFSET		0x400
-
-#define INF_REG_BASE			EXYNOS5420_INF_REG_BASE
-#define INF_REG0_OFFSET			0x00
-#define INF_REG1_OFFSET			0x04
-#define INF_REG2_OFFSET			0x08
-#define INF_REG3_OFFSET			0x0C
-#define INF_REG4_OFFSET			0x10
-#define INF_REG5_OFFSET			0x14
-#define INF_REG6_OFFSET			0x18
-#define INF_REG7_OFFSET			0x1C
-
-#define PMU_SPARE_BASE			(EXYNOS5420_INF_REG_BASE + 0x100)
-#define PMU_SPARE_0			PMU_SPARE_BASE
-#define PMU_SPARE_1			(PMU_SPARE_BASE + 0x4)
-#define PMU_SPARE_2			(PMU_SPARE_BASE + 0x8)
-#define PMU_SPARE_3			(PMU_SPARE_BASE + 0xc)
-#define RST_FLAG_REG			PMU_SPARE_BASE
 #define RST_FLAG_VAL			0xfcba0d10
 
-#define PAD_RETENTION_DRAM_STATUS	(EXYNOS5420_POWER_BASE + 0x3004)
-#define PAD_RETENTION_DRAM_COREBLK_OPTION	(EXYNOS5420_POWER_BASE + 0x31E8)
-#define PAD_RETENTION_DRAM_COREBLK_VAL	0x10000000
-
-#define samsung_get_base_adc() ((struct exynos5_adc *)EXYNOS5_ADC_BASE)
-#define samsung_get_base_clock() ((struct exynos5420_clock *)EXYNOS5_CLOCK_BASE)
-#define samsung_get_base_ace_sfr() ((struct exynos5_ace_sfr *)EXYNOS5_ACE_SFR_BASE)
-#define samsung_get_base_dsim() ((struct exynos5_dsim *)EXYNOS5_MIPI_DSI1_BASE)
-#define samsung_get_base_dp() ((struct exynos_dp *)EXYNOS5420_DP_BASE)
-#define samsung_get_base_disp_ctrl() ((struct exynos5_disp_ctrl *)EXYNOS5_DISP1_CTRL_BASE)
-#define samsung_get_base_fimd() ((struct exynos5_fimd *)EXYNOS5_FIMD_BASE)
-#define samsung_get_base_pro_id() ((struct exynos5_pro_id *)EXYNOS5_PRO_ID)
-
-#define samsung_get_base_mmc() ((struct exynos5_mmc *)EXYNOS5_MMC_BASE)
-#define samsung_get_base_mshci() ((struct exynos5_mshci *)EXYNOS5_MSHC_BASE)
-
-#define samsung_get_base_modem() ((struct exynos5_modem *)EXYNOS5_MODEM_BASE)
-#define samsung_get_base_sromc() ((struct exynos5_sromc *)EXYNOS5_SROMC_BASE)
-#define samsung_get_base_swreset() ((struct exynos5_swreset *)EXYNOS5_SWRESET)
-#define samsung_get_base_sysreg() ((struct exynos5_sysreg *)EXYNOS5_SYSREG_BASE)
-#define samsung_get_base_uart() ((struct exynos5_uart *)EXYNOS5_UART_BASE)
-#define samsung_get_base_usb_host_phy() ((struct exynos5_usb_host_phy *)EXYNOS5420_USB_HOST_PHY_BASE)
-#define samsung_get_base_usb_host_otg() ((struct exynos5_usb_host_otg *)EXYNOS5420_USB_HOST_OTG_BASE)
-#define samsung_get_base_watchdog() ((struct exynos5_watchdog *)EXYNOS5_WATCHDOG_BASE)
-#define samsung_get_base_power() ((struct exynos5_power *)EXYNOS5_POWER_BASE)
-#define samsung_get_base_i2s() ((struct exynos5_i2s *)EXYNOS5_I2S_BASE)
-#define samsung_get_base_spi0() ((struct exynos_spi *)EXYNOS5_SPI0_BASE)
-#define samsung_get_base_spi1() ((struct exynos_spi *)EXYNOS5_SPI1_BASE)
-#define samsung_get_base_spi2() ((struct exynos_spi *)EXYNOS5_SPI2_BASE)
-#define samsung_get_base_i2c() ((struct exynos5_i2c *)EXYNOS5_I2C_BASE)
-#define samsung_get_base_spi_isp() ((struct exynos5_spi_isp *)EXYNOS5_SPI_ISP_BASE)
-
 #define EXYNOS5_SPI_NUM_CONTROLLERS	5
 #define EXYNOS_I2C_MAX_CONTROLLERS	8
 
diff --git a/src/cpu/samsung/exynos5420/dmc.h b/src/cpu/samsung/exynos5420/dmc.h
index 1a6adca6f9..fa7482ae89 100644
--- a/src/cpu/samsung/exynos5420/dmc.h
+++ b/src/cpu/samsung/exynos5420/dmc.h
@@ -20,6 +20,8 @@
 
 #define DMC_INTERLEAVE_SIZE		0x1f
 
+#define PAD_RETENTION_DRAM_COREBLK_VAL	0x10000000
+
 /* CONCONTROL register fields */
 #define CONCONTROL_DFI_INIT_START_SHIFT	28
 #define CONCONTROL_RD_FETCH_SHIFT	12
@@ -69,6 +71,9 @@
 #define PHY_CON42_CTRL_RDLAT_MASK	(0x1f << PHY_CON42_CTRL_RDLAT_SHIFT)
 
 #ifndef __ASSEMBLER__
+
+#include "cpu.h"
+
 struct exynos5_dmc {
 	uint32_t concontrol;
 	uint32_t memcontrol;
@@ -202,6 +207,9 @@ struct exynos5_dmc {
 	uint32_t pmcnt3_ppc;	/* 0xe140 */
 } __attribute__((packed));
 
+static struct exynos5_dmc * const exynos_drex0 = (void *)EXYNOS5420_DMC_DREXI_0;
+static struct exynos5_dmc * const exynos_drex1 = (void *)EXYNOS5420_DMC_DREXI_1;
+
 struct exynos5_phy_control {
 	uint32_t phy_con0;
 	uint32_t phy_con1;
@@ -249,6 +257,11 @@ struct exynos5_phy_control {
 	uint32_t phy_con42;
 } __attribute__((packed));
 
+static struct exynos5_phy_control * const exynos_phy0_control =
+		(void *)EXYNOS5_DMC_PHY0_BASE;
+static struct exynos5_phy_control * const exynos_phy1_control =
+		(void *)EXYNOS5_DMC_PHY1_BASE;
+
 struct exynos5_tzasc {
 	uint8_t res1[0xf00];
 	uint32_t membaseconfig0;
@@ -258,6 +271,11 @@ struct exynos5_tzasc {
 	uint32_t memconfig1;
 } __attribute__((packed));
 
+static struct exynos5_tzasc * const exynos_tzasc0 =
+		(void *)EXYNOS5420_DMC_TZASC_0;
+static struct exynos5_tzasc * const exynos_tzasc1 =
+		(void *)EXYNOS5420_DMC_TZASC_1;
+
 enum ddr_mode {
 	/* This is in order of ctrl_ddr_mode values. Do not change. */
 	DDR_MODE_DDR2	= 0x0,
diff --git a/src/cpu/samsung/exynos5420/dmc_init_ddr3.c b/src/cpu/samsung/exynos5420/dmc_init_ddr3.c
index 2dc03b3add..4acf7d13f3 100644
--- a/src/cpu/samsung/exynos5420/dmc_init_ddr3.c
+++ b/src/cpu/samsung/exynos5420/dmc_init_ddr3.c
@@ -24,13 +24,13 @@
  * MA 02111-1307 USA
  */
 
-#include <console/console.h>
 #include <delay.h>
 #include <arch/io.h>
+#include <console/console.h>
+#include "clk.h"
 #include "dmc.h"
+#include "power.h"
 #include "setup.h"
-#include "cpu.h"
-#include "clk.h"
 
 #define TIMEOUT	10000
 
@@ -38,61 +38,49 @@
 
 int ddr3_mem_ctrl_init(struct mem_timings *mem, int interleave_size, int reset)
 {
-	struct exynos5420_clock *clk =
-		(struct exynos5420_clock *)EXYNOS5_CLOCK_BASE;
-	struct exynos5_phy_control *phy0_ctrl, *phy1_ctrl;
-	struct exynos5_dmc *drex0, *drex1;
-	struct exynos5_tzasc *tzasc0, *tzasc1;
 	u32 val, nLockR, nLockW_phy0, nLockW_phy1;
 	int i, chip;
 
-	phy0_ctrl = (struct exynos5_phy_control *)EXYNOS5_DMC_PHY0_BASE;
-	phy1_ctrl = (struct exynos5_phy_control *)EXYNOS5_DMC_PHY1_BASE;
-	drex0 = (struct exynos5_dmc *)EXYNOS5420_DMC_DREXI_0;
-	drex1 = (struct exynos5_dmc *)EXYNOS5420_DMC_DREXI_1;
-	tzasc0 = (struct exynos5_tzasc *)EXYNOS5420_DMC_TZASC_0;
-	tzasc1 = (struct exynos5_tzasc *)EXYNOS5420_DMC_TZASC_1;
-
 	/* Enable PAUSE for DREX */
-	setbits_le32(&clk->pause, ENABLE_BIT);
+	setbits_le32(&exynos_clock->pause, ENABLE_BIT);
 
 	/* Enable BYPASS mode */
-	setbits_le32(&clk->bpll_con1, BYPASS_EN);
+	setbits_le32(&exynos_clock->bpll_con1, BYPASS_EN);
 
-	writel(MUX_BPLL_SEL_FOUTBPLL, &clk->clk_src_cdrex);
+	writel(MUX_BPLL_SEL_FOUTBPLL, &exynos_clock->clk_src_cdrex);
 	do {
-		val = readl(&clk->clk_mux_stat_cdrex);
+		val = readl(&exynos_clock->clk_mux_stat_cdrex);
 		val &= BPLL_SEL_MASK;
 	} while (val != FOUTBPLL);
 
-	clrbits_le32(&clk->bpll_con1, BYPASS_EN);
+	clrbits_le32(&exynos_clock->bpll_con1, BYPASS_EN);
 
 	/* Specify the DDR memory type as DDR3 */
-	val = readl(&phy0_ctrl->phy_con0);
+	val = readl(&exynos_phy0_control->phy_con0);
 	val &= ~(PHY_CON0_CTRL_DDR_MODE_MASK << PHY_CON0_CTRL_DDR_MODE_SHIFT);
 	val |= (mem->mem_type << PHY_CON0_CTRL_DDR_MODE_SHIFT);
-	writel(val, &phy0_ctrl->phy_con0);
+	writel(val, &exynos_phy0_control->phy_con0);
 
-	val = readl(&phy1_ctrl->phy_con0);
+	val = readl(&exynos_phy1_control->phy_con0);
 	val &= ~(PHY_CON0_CTRL_DDR_MODE_MASK << PHY_CON0_CTRL_DDR_MODE_SHIFT);
 	val |= (mem->mem_type << PHY_CON0_CTRL_DDR_MODE_SHIFT);
-	writel(val, &phy1_ctrl->phy_con0);
+	writel(val, &exynos_phy1_control->phy_con0);
 
 	/* Set Read Latency and Burst Length for PHY0 and PHY1 */
 	val = (mem->ctrl_bstlen << PHY_CON42_CTRL_BSTLEN_SHIFT) |
 		(mem->ctrl_rdlat << PHY_CON42_CTRL_RDLAT_SHIFT);
-	writel(val, &phy0_ctrl->phy_con42);
-	writel(val, &phy1_ctrl->phy_con42);
+	writel(val, &exynos_phy0_control->phy_con42);
+	writel(val, &exynos_phy1_control->phy_con42);
 
-	val = readl(&phy0_ctrl->phy_con26);
+	val = readl(&exynos_phy0_control->phy_con26);
 	val &= ~(T_WRDATA_EN_MASK << T_WRDATA_EN_OFFSET);
 	val |= (T_WRDATA_EN_DDR3 << T_WRDATA_EN_OFFSET);
-	writel(val, &phy0_ctrl->phy_con26);
+	writel(val, &exynos_phy0_control->phy_con26);
 
-	val = readl(&phy1_ctrl->phy_con26);
+	val = readl(&exynos_phy1_control->phy_con26);
 	val &= ~(T_WRDATA_EN_MASK << T_WRDATA_EN_OFFSET);
 	val |= (T_WRDATA_EN_DDR3 << T_WRDATA_EN_OFFSET);
-	writel(val, &phy1_ctrl->phy_con26);
+	writel(val, &exynos_phy1_control->phy_con26);
 
 	/* Set Driver strength for CK, CKE, CS & CA to 0x7
 	 * Set Driver strength for Data Slice 0~3 to 0x6
@@ -101,86 +89,86 @@ int ddr3_mem_ctrl_init(struct mem_timings *mem, int interleave_size, int reset)
 		(0x7 << CA_CS_DRVR_DS_OFFSET) | (0x7 << CA_ADR_DRVR_DS_OFFSET);
 	val |= (0x7 << DA_3_DS_OFFSET) | (0x7 << DA_2_DS_OFFSET) |
 		(0x7 << DA_1_DS_OFFSET) | (0x7 << DA_0_DS_OFFSET);
-	writel(val, &phy0_ctrl->phy_con39);
-	writel(val, &phy1_ctrl->phy_con39);
+	writel(val, &exynos_phy0_control->phy_con39);
+	writel(val, &exynos_phy1_control->phy_con39);
 
 	/* ZQ Calibration */
-	if (dmc_config_zq(mem, phy0_ctrl, phy1_ctrl))
+	if (dmc_config_zq(mem, exynos_phy0_control, exynos_phy1_control))
 		return SETUP_ERR_ZQ_CALIBRATION_FAILURE;
 
-	clrbits_le32(&phy0_ctrl->phy_con16, ZQ_CLK_DIV_EN);
-	clrbits_le32(&phy1_ctrl->phy_con16, ZQ_CLK_DIV_EN);
+	clrbits_le32(&exynos_phy0_control->phy_con16, ZQ_CLK_DIV_EN);
+	clrbits_le32(&exynos_phy1_control->phy_con16, ZQ_CLK_DIV_EN);
 
 	/* DQ Signal */
-	val = readl(&phy0_ctrl->phy_con14);
+	val = readl(&exynos_phy0_control->phy_con14);
 	val |= mem->phy0_pulld_dqs;
-	writel(val, &phy0_ctrl->phy_con14);
-	val = readl(&phy1_ctrl->phy_con14);
+	writel(val, &exynos_phy0_control->phy_con14);
+	val = readl(&exynos_phy1_control->phy_con14);
 	val |= mem->phy1_pulld_dqs;
-	writel(val, &phy1_ctrl->phy_con14);
+	writel(val, &exynos_phy1_control->phy_con14);
 
 	val = MEM_TERM_EN | PHY_TERM_EN;
-	writel(val, &drex0->phycontrol0);
-	writel(val, &drex1->phycontrol0);
+	writel(val, &exynos_drex0->phycontrol0);
+	writel(val, &exynos_drex1->phycontrol0);
 
 	writel(mem->concontrol |
 		(mem->dfi_init_start << CONCONTROL_DFI_INIT_START_SHIFT) |
 		(mem->rd_fetch << CONCONTROL_RD_FETCH_SHIFT),
-		&drex0->concontrol);
+		&exynos_drex0->concontrol);
 	writel(mem->concontrol |
 		(mem->dfi_init_start << CONCONTROL_DFI_INIT_START_SHIFT) |
 		(mem->rd_fetch << CONCONTROL_RD_FETCH_SHIFT),
-		&drex1->concontrol);
+		&exynos_drex1->concontrol);
 
 	do {
-		val = readl(&drex0->phystatus);
+		val = readl(&exynos_drex0->phystatus);
 	} while ((val & DFI_INIT_COMPLETE) != DFI_INIT_COMPLETE);
 	do {
-		val = readl(&drex1->phystatus);
+		val = readl(&exynos_drex1->phystatus);
 	} while ((val & DFI_INIT_COMPLETE) != DFI_INIT_COMPLETE);
 
-	clrbits_le32(&drex0->concontrol, DFI_INIT_START);
-	clrbits_le32(&drex1->concontrol, DFI_INIT_START);
+	clrbits_le32(&exynos_drex0->concontrol, DFI_INIT_START);
+	clrbits_le32(&exynos_drex1->concontrol, DFI_INIT_START);
 
-	update_reset_dll(drex0, mem->mem_type);
-	update_reset_dll(drex1, mem->mem_type);
+	update_reset_dll(exynos_drex0, mem->mem_type);
+	update_reset_dll(exynos_drex1, mem->mem_type);
 
 	/* MEMBASECONFIG0 (CS0) */
-	writel(mem->membaseconfig0, &tzasc0->membaseconfig0);
-	writel(mem->membaseconfig0, &tzasc1->membaseconfig0);
+	writel(mem->membaseconfig0, &exynos_tzasc0->membaseconfig0);
+	writel(mem->membaseconfig0, &exynos_tzasc1->membaseconfig0);
 
 	/* MEMBASECONFIG1 (CS1) */
 	if (mem->chips_per_channel == 2) {
-		writel(mem->membaseconfig1, &tzasc0->membaseconfig1);
-		writel(mem->membaseconfig1, &tzasc1->membaseconfig1);
+		writel(mem->membaseconfig1, &exynos_tzasc0->membaseconfig1);
+		writel(mem->membaseconfig1, &exynos_tzasc1->membaseconfig1);
 	}
 
 	/* Memory Channel Inteleaving Size
 	 * Exynos5420 Channel interleaving = 128 bytes
 	 */
 	/* MEMCONFIG0/1 */
-	writel(mem->memconfig, &tzasc0->memconfig0);
-	writel(mem->memconfig, &tzasc1->memconfig0);
-	writel(mem->memconfig, &tzasc0->memconfig1);
-	writel(mem->memconfig, &tzasc1->memconfig1);
+	writel(mem->memconfig, &exynos_tzasc0->memconfig0);
+	writel(mem->memconfig, &exynos_tzasc1->memconfig0);
+	writel(mem->memconfig, &exynos_tzasc0->memconfig1);
+	writel(mem->memconfig, &exynos_tzasc1->memconfig1);
 
 	/* Precharge Configuration */
 	writel(mem->prechconfig_tp_cnt << PRECHCONFIG_TP_CNT_SHIFT,
-		&drex0->prechconfig0);
+		&exynos_drex0->prechconfig0);
 	writel(mem->prechconfig_tp_cnt << PRECHCONFIG_TP_CNT_SHIFT,
-		&drex1->prechconfig0);
+		&exynos_drex1->prechconfig0);
 
 	/* TimingRow, TimingData, TimingPower and Timingaref
 	 * values as per Memory AC parameters
 	 */
-	writel(mem->timing_ref, &drex0->timingref);
-	writel(mem->timing_ref, &drex1->timingref);
-	writel(mem->timing_row, &drex0->timingrow);
-	writel(mem->timing_row, &drex1->timingrow);
-	writel(mem->timing_data, &drex0->timingdata);
-	writel(mem->timing_data, &drex1->timingdata);
-	writel(mem->timing_power, &drex0->timingpower);
-	writel(mem->timing_power, &drex1->timingpower);
+	writel(mem->timing_ref, &exynos_drex0->timingref);
+	writel(mem->timing_ref, &exynos_drex1->timingref);
+	writel(mem->timing_row, &exynos_drex0->timingrow);
+	writel(mem->timing_row, &exynos_drex1->timingrow);
+	writel(mem->timing_data, &exynos_drex0->timingdata);
+	writel(mem->timing_data, &exynos_drex1->timingdata);
+	writel(mem->timing_power, &exynos_drex0->timingpower);
+	writel(mem->timing_power, &exynos_drex1->timingpower);
 
 	if (reset) {
 		/* Send NOP, MRS and ZQINIT commands.
@@ -188,8 +176,8 @@ int ddr3_mem_ctrl_init(struct mem_timings *mem, int interleave_size, int reset)
 		 * reseting the DRAM after resume, this will lead to memory
 		 * corruption as DRAM content is lost after DRAM reset.
 		 */
-		dmc_config_mrs(mem, drex0);
-		dmc_config_mrs(mem, drex1);
+		dmc_config_mrs(mem, exynos_drex0);
+		dmc_config_mrs(mem, exynos_drex1);
 	} else {
 		u32 ret;
 
@@ -202,9 +190,9 @@ int ddr3_mem_ctrl_init(struct mem_timings *mem, int interleave_size, int reset)
 		 * initialization is complete.
 		 */
 		write32(PAD_RETENTION_DRAM_COREBLK_VAL,
-			(void *)PAD_RETENTION_DRAM_COREBLK_OPTION);
+			&exynos_power->padret_dram_cblk_opt);
 		do {
-			ret = read32((void *)PAD_RETENTION_DRAM_STATUS);
+			ret = read32(&exynos_power->padret_dram_status);
 		} while (ret != 0x1);
 
 		/*
@@ -215,75 +203,75 @@ int ddr3_mem_ctrl_init(struct mem_timings *mem, int interleave_size, int reset)
 			for (chip = 0; chip < mem->chips_to_configure; chip++) {
 				writel(DIRECT_CMD_REFA |
 					(chip << DIRECT_CMD_CHIP_SHIFT),
-					&drex0->directcmd);
+					&exynos_drex0->directcmd);
 				writel(DIRECT_CMD_REFA |
 					(chip << DIRECT_CMD_CHIP_SHIFT),
-					&drex1->directcmd);
+					&exynos_drex1->directcmd);
 			}
 		}
 	}
 
 	if (mem->gate_leveling_enable) {
 
-		writel(PHY_CON0_RESET_VAL, &phy0_ctrl->phy_con0);
-		writel(PHY_CON0_RESET_VAL, &phy1_ctrl->phy_con0);
+		writel(PHY_CON0_RESET_VAL, &exynos_phy0_control->phy_con0);
+		writel(PHY_CON0_RESET_VAL, &exynos_phy1_control->phy_con0);
 
-		setbits_le32(&phy0_ctrl->phy_con0, P0_CMD_EN);
-		setbits_le32(&phy1_ctrl->phy_con0, P0_CMD_EN);
+		setbits_le32(&exynos_phy0_control->phy_con0, P0_CMD_EN);
+		setbits_le32(&exynos_phy1_control->phy_con0, P0_CMD_EN);
 
 		val = PHY_CON2_RESET_VAL;
 		val |= INIT_DESKEW_EN;
-		writel(val, &phy0_ctrl->phy_con2);
-		writel(val, &phy1_ctrl->phy_con2);
+		writel(val, &exynos_phy0_control->phy_con2);
+		writel(val, &exynos_phy1_control->phy_con2);
 
-		val =  readl(&phy0_ctrl->phy_con1);
+		val =  readl(&exynos_phy0_control->phy_con1);
 		val |= (RDLVL_PASS_ADJ_VAL << RDLVL_PASS_ADJ_OFFSET);
-		writel(val, &phy0_ctrl->phy_con1);
+		writel(val, &exynos_phy0_control->phy_con1);
 
-		val =  readl(&phy1_ctrl->phy_con1);
+		val =  readl(&exynos_phy1_control->phy_con1);
 		val |= (RDLVL_PASS_ADJ_VAL << RDLVL_PASS_ADJ_OFFSET);
-		writel(val, &phy1_ctrl->phy_con1);
+		writel(val, &exynos_phy1_control->phy_con1);
 
-		nLockR = readl(&phy0_ctrl->phy_con13);
+		nLockR = readl(&exynos_phy0_control->phy_con13);
 		nLockW_phy0 = (nLockR & CTRL_LOCK_COARSE_MASK) >> 2;
-		nLockR = readl(&phy0_ctrl->phy_con12);
+		nLockR = readl(&exynos_phy0_control->phy_con12);
 		nLockR &= ~CTRL_DLL_ON;
 		nLockR |= nLockW_phy0;
-		writel(nLockR, &phy0_ctrl->phy_con12);
+		writel(nLockR, &exynos_phy0_control->phy_con12);
 
-		nLockR = readl(&phy1_ctrl->phy_con13);
+		nLockR = readl(&exynos_phy1_control->phy_con13);
 		nLockW_phy1 = (nLockR & CTRL_LOCK_COARSE_MASK) >> 2;
-		nLockR = readl(&phy1_ctrl->phy_con12);
+		nLockR = readl(&exynos_phy1_control->phy_con12);
 		nLockR &= ~CTRL_DLL_ON;
 		nLockR |= nLockW_phy1;
-		writel(nLockR, &phy1_ctrl->phy_con12);
+		writel(nLockR, &exynos_phy1_control->phy_con12);
 
 		val = (0x3 << DIRECT_CMD_BANK_SHIFT) | 0x4;
 		for (chip = 0; chip < mem->chips_to_configure; chip++) {
 			writel(val | (chip << DIRECT_CMD_CHIP_SHIFT),
-				&drex0->directcmd);
+				&exynos_drex0->directcmd);
 			writel(val | (chip << DIRECT_CMD_CHIP_SHIFT),
-				&drex1->directcmd);
+				&exynos_drex1->directcmd);
 		}
 
-		setbits_le32(&phy0_ctrl->phy_con2, RDLVL_GATE_EN);
-		setbits_le32(&phy1_ctrl->phy_con2, RDLVL_GATE_EN);
+		setbits_le32(&exynos_phy0_control->phy_con2, RDLVL_GATE_EN);
+		setbits_le32(&exynos_phy1_control->phy_con2, RDLVL_GATE_EN);
 
-		setbits_le32(&phy0_ctrl->phy_con0, CTRL_SHGATE);
-		setbits_le32(&phy1_ctrl->phy_con0, CTRL_SHGATE);
+		setbits_le32(&exynos_phy0_control->phy_con0, CTRL_SHGATE);
+		setbits_le32(&exynos_phy1_control->phy_con0, CTRL_SHGATE);
 
-		val = readl(&phy0_ctrl->phy_con1);
+		val = readl(&exynos_phy0_control->phy_con1);
 		val &= ~(CTRL_GATEDURADJ_MASK);
-		writel(val, &phy0_ctrl->phy_con1);
+		writel(val, &exynos_phy0_control->phy_con1);
 
-		val = readl(&phy1_ctrl->phy_con1);
+		val = readl(&exynos_phy1_control->phy_con1);
 		val &= ~(CTRL_GATEDURADJ_MASK);
-		writel(val, &phy1_ctrl->phy_con1);
+		writel(val, &exynos_phy1_control->phy_con1);
 
-		writel(CTRL_RDLVL_GATE_ENABLE, &drex0->rdlvl_config);
+		writel(CTRL_RDLVL_GATE_ENABLE, &exynos_drex0->rdlvl_config);
 		i = TIMEOUT;
-		while (((readl(&drex0->phystatus) & RDLVL_COMPLETE_CHO) !=
-			RDLVL_COMPLETE_CHO) && (i > 0)) {
+		while (((readl(&exynos_drex0->phystatus) & RDLVL_COMPLETE_CHO)
+			!= RDLVL_COMPLETE_CHO) && (i > 0)) {
 			/*
 			 * TODO(waihong): Comment on how long this take to
 			 * timeout
@@ -293,12 +281,12 @@ int ddr3_mem_ctrl_init(struct mem_timings *mem, int interleave_size, int reset)
 		}
 		if (!i)
 			return SETUP_ERR_RDLV_COMPLETE_TIMEOUT;
-		writel(CTRL_RDLVL_GATE_DISABLE, &drex0->rdlvl_config);
+		writel(CTRL_RDLVL_GATE_DISABLE, &exynos_drex0->rdlvl_config);
 
-		writel(CTRL_RDLVL_GATE_ENABLE, &drex1->rdlvl_config);
+		writel(CTRL_RDLVL_GATE_ENABLE, &exynos_drex1->rdlvl_config);
 		i = TIMEOUT;
-		while (((readl(&drex1->phystatus) & RDLVL_COMPLETE_CHO) !=
-			RDLVL_COMPLETE_CHO) && (i > 0)) {
+		while (((readl(&exynos_drex1->phystatus) & RDLVL_COMPLETE_CHO)
+			!= RDLVL_COMPLETE_CHO) && (i > 0)) {
 			/*
 			 * TODO(waihong): Comment on how long this take to
 			 * timeout
@@ -308,34 +296,34 @@ int ddr3_mem_ctrl_init(struct mem_timings *mem, int interleave_size, int reset)
 		}
 		if (!i)
 			return SETUP_ERR_RDLV_COMPLETE_TIMEOUT;
-		writel(CTRL_RDLVL_GATE_DISABLE, &drex1->rdlvl_config);
+		writel(CTRL_RDLVL_GATE_DISABLE, &exynos_drex1->rdlvl_config);
 
-		writel(0, &phy0_ctrl->phy_con14);
-		writel(0, &phy1_ctrl->phy_con14);
+		writel(0, &exynos_phy0_control->phy_con14);
+		writel(0, &exynos_phy1_control->phy_con14);
 
 		val = (0x3 << DIRECT_CMD_BANK_SHIFT);
 		for (chip = 0; chip < mem->chips_to_configure; chip++) {
 			writel(val | (chip << DIRECT_CMD_CHIP_SHIFT),
-				&drex0->directcmd);
+				&exynos_drex0->directcmd);
 			writel(val | (chip << DIRECT_CMD_CHIP_SHIFT),
-				&drex1->directcmd);
+				&exynos_drex1->directcmd);
 		}
 
 		/* Common Settings for Leveling */
 		val = PHY_CON12_RESET_VAL;
-		writel((val + nLockW_phy0), &phy0_ctrl->phy_con12);
-		writel((val + nLockW_phy1), &phy1_ctrl->phy_con12);
+		writel((val + nLockW_phy0), &exynos_phy0_control->phy_con12);
+		writel((val + nLockW_phy1), &exynos_phy1_control->phy_con12);
 
-		setbits_le32(&phy0_ctrl->phy_con2, DLL_DESKEW_EN);
-		setbits_le32(&phy1_ctrl->phy_con2, DLL_DESKEW_EN);
+		setbits_le32(&exynos_phy0_control->phy_con2, DLL_DESKEW_EN);
+		setbits_le32(&exynos_phy1_control->phy_con2, DLL_DESKEW_EN);
 	}
 
 	/* Send PALL command */
-	dmc_config_prech(mem, drex0);
-	dmc_config_prech(mem, drex1);
+	dmc_config_prech(mem, exynos_drex0);
+	dmc_config_prech(mem, exynos_drex1);
 
-	writel(mem->memcontrol, &drex0->memcontrol);
-	writel(mem->memcontrol, &drex1->memcontrol);
+	writel(mem->memcontrol, &exynos_drex0->memcontrol);
+	writel(mem->memcontrol, &exynos_drex1->memcontrol);
 
 	/*
 	 * Set DMC Concontrol: Enable auto-refresh counter, provide
@@ -345,18 +333,18 @@ int ddr3_mem_ctrl_init(struct mem_timings *mem, int interleave_size, int reset)
 	writel(mem->concontrol | (mem->aref_en << CONCONTROL_AREF_EN_SHIFT) |
 		(mem->rd_fetch << CONCONTROL_RD_FETCH_SHIFT)|
 		DMC_CONCONTROL_IO_PD_CON(0x2),
-		&drex0->concontrol);
+		&exynos_drex0->concontrol);
 	writel(mem->concontrol | (mem->aref_en << CONCONTROL_AREF_EN_SHIFT) |
 		(mem->rd_fetch << CONCONTROL_RD_FETCH_SHIFT)|
 		DMC_CONCONTROL_IO_PD_CON(0x2),
-		&drex1->concontrol);
+		&exynos_drex1->concontrol);
 
 	/* Enable Clock Gating Control for DMC
 	 * this saves around 25 mw dmc power as compared to the power
 	 * consumption without these bits enabled
 	 */
-	setbits_le32(&drex0->cgcontrol, DMC_INTERNAL_CG);
-	setbits_le32(&drex1->cgcontrol, DMC_INTERNAL_CG);
+	setbits_le32(&exynos_drex0->cgcontrol, DMC_INTERNAL_CG);
+	setbits_le32(&exynos_drex1->cgcontrol, DMC_INTERNAL_CG);
 
 	return 0;
 }
diff --git a/src/cpu/samsung/exynos5420/dp.c b/src/cpu/samsung/exynos5420/dp.c
index c1fa17a9c6..b147035b64 100644
--- a/src/cpu/samsung/exynos5420/dp.c
+++ b/src/cpu/samsung/exynos5420/dp.c
@@ -27,15 +27,12 @@
 #include <console/console.h>
 #include <lib.h>
 #include "timer.h"
-#include "cpu.h"
 #include "power.h"
 #include "sysreg.h"
-#include <drivers/maxim/max77686/max77686.h>
 
-#include "device/i2c.h"
-#include "i2c.h"
-#include "fimd.h"
 #include "dp.h"
+#include "fimd.h"
+#include "i2c.h"
 
 /*
  * Here is the rough outline of how we bring up the display:
diff --git a/src/cpu/samsung/exynos5420/dp.h b/src/cpu/samsung/exynos5420/dp.h
index 4d9d26b859..9131b0853c 100644
--- a/src/cpu/samsung/exynos5420/dp.h
+++ b/src/cpu/samsung/exynos5420/dp.h
@@ -23,6 +23,8 @@
 #ifndef CPU_SAMSUNG_EXYNOS5420_DP_H
 #define CPU_SAMSUNG_EXYNOS5420_DP_H
 
+#include "cpu.h"
+
 /* DSIM register map */
 struct exynos_dp {
 	u8	res1[0x10];
@@ -209,6 +211,9 @@ struct exynos_dp {
 	u32	test_pattern_gen_ctrl;
 };
 
+static struct exynos_dp * const exynos_dp0 = (void *)EXYNOS5_DP0_BASE;
+static struct exynos_dp * const exynos_dp1 = (void *)EXYNOS5_DP1_BASE;
+
 /* For DP VIDEO CTL 1 */
 #define VIDEO_EN_MASK				(0x01 << 7)
 #define VIDEO_MUTE_MASK				(0x01 << 6)
diff --git a/src/cpu/samsung/exynos5420/dp_lowlevel.c b/src/cpu/samsung/exynos5420/dp_lowlevel.c
index 16b9a7ffb2..2b2418ec21 100644
--- a/src/cpu/samsung/exynos5420/dp_lowlevel.c
+++ b/src/cpu/samsung/exynos5420/dp_lowlevel.c
@@ -19,27 +19,21 @@
  * MA 02111-1307 USA
  */
 
-#include <arch/io.h>
+#include <delay.h>
 #include <stdlib.h>
 #include <string.h>
 #include <timer.h>
-#include <delay.h>
+#include <arch/io.h>
 #include <console/console.h>
-#include "timer.h"
-#include "cpu.h"
+#include "dp.h"
+#include "fimd.h"
+#include "i2c.h"
 #include "power.h"
 #include "sysreg.h"
-#include <drivers/maxim/max77686/max77686.h>
-
-#include "device/i2c.h"
-#include "i2c.h"
-#include "fimd.h"
-#include "dp.h"
+#include "timer.h"
 
-/* in u-boot, there's a function you call to set a pointer
- * to a constant. Klever!
- */
-struct exynos_dp *dp_regs = samsung_get_base_dp();
+/* FIXME: I think the DP controller shouldn't be hardcoded here... */
+static struct exynos_dp * const dp_regs = (void *)EXYNOS5_DP1_BASE;
 
 /* for debugging, it's nice to get control on a per-file basis.
  * I had a bit of a discussion with myself (boring!) about
@@ -1188,12 +1182,11 @@ unsigned int exynos_dp_is_video_stream_on(void)
 void dp_phy_control(unsigned int enable)
 {
 	u32 cfg;
-	struct exynos5_power *power = samsung_get_base_power();
 
-	cfg = lread32(&power->dptx_phy_control);
+	cfg = lread32(&exynos_power->dptx_phy_control);
 	if (enable)
 		cfg |= EXYNOS_DP_PHY_ENABLE;
 	else
 		cfg &= ~EXYNOS_DP_PHY_ENABLE;
-	lwrite32(cfg, &power->dptx_phy_control);
+	lwrite32(cfg, &exynos_power->dptx_phy_control);
 }
diff --git a/src/cpu/samsung/exynos5420/fimd.c b/src/cpu/samsung/exynos5420/fimd.c
index b94148a6b1..1e51712e53 100644
--- a/src/cpu/samsung/exynos5420/fimd.c
+++ b/src/cpu/samsung/exynos5420/fimd.c
@@ -20,31 +20,15 @@
  * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
  */
 
-#include <console/console.h>
-#include <arch/io.h>
 #include <delay.h>
-#include "timer.h"
+#include <arch/io.h>
+#include <console/console.h>
 #include "clk.h"
-#include "cpu.h"
-#include "periph.h"
 #include "dp.h"
 #include "fimd.h"
+#include "periph.h"
 #include "sysreg.h"
-
-/* left here because it's a counterexample of good style.  u-boot
- * likes to call a function to get a base address. To get that they
- * walk the device tree several times. It's costly. So they turn a
- * known-at-build-time constant into a bunch of function calls. What
- * to do about this inefficiency? Fix the inefficiency? No, scarf
- * variables away in global memory of course, and remove all hope of
- * optimization. Bad idea.
- *
- * the u-boot sources that define fimd base are ... bizarre. I'm going
- * with a hardcoded hack until we get this working. FIXME.
- *
- * static struct exynos_fb *fimd_ctrl * =
- * (void *)0x14400000; //samsung_get_base_fimd();
- */
+#include "timer.h"
 
 /* fairly useful debugging stuff. */
 #if 0
@@ -70,7 +54,6 @@ static inline unsigned long fradl(void *v) {
 /* not sure where we want this so ... */
 static unsigned long get_lcd_clk(void)
 {
-	struct exynos5420_clock *clk = samsung_get_base_clock();
 	u32 pclk, sclk;
 	unsigned int sel;
 	unsigned int ratio;
@@ -81,7 +64,7 @@ static unsigned long get_lcd_clk(void)
 	 * 0: SCLK_RPLL
 	 * 1: SCLK_SPLL
 	 */
-	sel = lreadl(&clk->clk_src_disp10);
+	sel = lreadl(&exynos_clock->clk_src_disp10);
 	sel &= (1 << 4);
 
 	if (sel){
@@ -94,7 +77,7 @@ static unsigned long get_lcd_clk(void)
 	 * CLK_DIV_DISP10
 	 * FIMD1_RATIO [3:0]
 	 */
-	ratio = lreadl(&clk->clk_div_disp10);
+	ratio = lreadl(&exynos_clock->clk_div_disp10);
 	ratio = ratio & 0xf;
 
 	pclk = sclk / (ratio + 1);
@@ -325,7 +308,6 @@ void exynos_fimd_window_off(unsigned int win_id)
 
 static void exynos5_set_system_display(void)
 {
-        struct exynos5_sysreg *sysreg = samsung_get_base_sysreg();
         unsigned int cfg = 0;
 
         /*
@@ -333,9 +315,9 @@ static void exynos5_set_system_display(void)
          * 0: MIE/MDNIE
          * 1: FIMD Bypass
          */
-        cfg = lreadl(&sysreg->disp1blk_cfg);
+        cfg = lreadl(&exynos_sysreg->disp1blk_cfg);
         cfg |= (1 << 15);
-        lwritel(cfg, &sysreg->disp1blk_cfg);
+        lwritel(cfg, &exynos_sysreg->disp1blk_cfg);
 }
 
 void exynos_fimd_lcd_init(vidinfo_t *vid)
diff --git a/src/cpu/samsung/exynos5420/fimd.h b/src/cpu/samsung/exynos5420/fimd.h
index 7d6897958b..ce8773fd17 100644
--- a/src/cpu/samsung/exynos5420/fimd.h
+++ b/src/cpu/samsung/exynos5420/fimd.h
@@ -22,6 +22,8 @@
 #ifndef CPU_SAMSUNG_EXYNOS5420_FIMD_H
 #define CPU_SAMSUNG_EXYNOS5420_FIMD_H
 
+#include "cpu.h"
+
 /* FIMD register map */
 struct exynos5_fimd {
 	/* This is an incomplete list. Add registers as and when required */
diff --git a/src/cpu/samsung/exynos5420/gpio.c b/src/cpu/samsung/exynos5420/gpio.c
index b17ff40d55..2b65eda04e 100644
--- a/src/cpu/samsung/exynos5420/gpio.c
+++ b/src/cpu/samsung/exynos5420/gpio.c
@@ -44,12 +44,12 @@ struct gpio_info {
 };
 
 static const struct gpio_info gpio_data[EXYNOS_GPIO_NUM_PARTS] = {
-	{ EXYNOS5_GPIO_PART1_BASE, GPIO_MAX_PORT_PART_1 },
-	{ EXYNOS5_GPIO_PART2_BASE, GPIO_MAX_PORT_PART_2 },
-	{ EXYNOS5_GPIO_PART3_BASE, GPIO_MAX_PORT_PART_3 },
-	{ EXYNOS5_GPIO_PART4_BASE, GPIO_MAX_PORT_PART_4 },
-	{ EXYNOS5_GPIO_PART5_BASE, GPIO_MAX_PORT_PART_5 },
-	{ EXYNOS5_GPIO_PART6_BASE, GPIO_MAX_PORT },
+	{ EXYNOS5420_GPIO_PART1_BASE, GPIO_MAX_PORT_PART_1 },
+	{ EXYNOS5420_GPIO_PART2_BASE, GPIO_MAX_PORT_PART_2 },
+	{ EXYNOS5420_GPIO_PART3_BASE, GPIO_MAX_PORT_PART_3 },
+	{ EXYNOS5420_GPIO_PART4_BASE, GPIO_MAX_PORT_PART_4 },
+	{ EXYNOS5420_GPIO_PART5_BASE, GPIO_MAX_PORT_PART_5 },
+	{ EXYNOS5420_GPIO_PART6_BASE, GPIO_MAX_PORT },
 };
 
 /* This macro gets gpio pin offset from 0..7 */
diff --git a/src/cpu/samsung/exynos5420/gpio.h b/src/cpu/samsung/exynos5420/gpio.h
index 0011904eb5..4cf8e57249 100644
--- a/src/cpu/samsung/exynos5420/gpio.h
+++ b/src/cpu/samsung/exynos5420/gpio.h
@@ -20,6 +20,8 @@
 #ifndef CPU_SAMSUNG_EXYNOS5420_GPIO_H
 #define CPU_SAMSUNG_EXYNOS5420_GPIO_H
 
+#include "cpu.h"
+
 struct gpio_bank {
 	unsigned int	con;
 	unsigned int	dat;
@@ -52,73 +54,57 @@ struct gpio_bank {
 #define GPIO_DRV_FAST	0x0
 #define GPIO_DRV_SLOW	0x1
 
-#define EXYNOS5_GPIO_BASE0	0x13400000
-#define EXYNOS5_GPIO_BASE1	0x13400c00
-#define EXYNOS5_GPIO_BASE2	0x13410000
-#define EXYNOS5_GPIO_BASE3	0x14000000
-#define EXYNOS5_GPIO_BASE4	0x14010000
-#define EXYNOS5_GPIO_BASE5	0x03860000
-
 enum exynos5_gpio_port {
-	/*
-	 * Ordered by base address + offset.
-	 * ETC registers are special, thus not included.
-	 */
-
-	/* base == EXYNOS_GPIO_BASE0 */
-	EXYNOS5_GPY7 = EXYNOS5_GPIO_BASE0 + 0x0000,
-
-	/* base == EXYNOS_GPIO_BASE1 */
-	EXYNOS5_GPX0 = EXYNOS5_GPIO_BASE1 + 0x0000,
-	EXYNOS5_GPX1 = EXYNOS5_GPIO_BASE1 + 0x0020,
-	EXYNOS5_GPX2 = EXYNOS5_GPIO_BASE1 + 0x0040,
-	EXYNOS5_GPX3 = EXYNOS5_GPIO_BASE1 + 0x0060,
-
-	/* base == EXYNOS_GPIO_BASE2 */
-	EXYNOS5_GPC0 = EXYNOS5_GPIO_BASE2 + 0x0000,
-	EXYNOS5_GPC1 = EXYNOS5_GPIO_BASE2 + 0x0020,
-	EXYNOS5_GPC2 = EXYNOS5_GPIO_BASE2 + 0x0040,
-	EXYNOS5_GPC3 = EXYNOS5_GPIO_BASE2 + 0x0060,
-	EXYNOS5_GPC4 = EXYNOS5_GPIO_BASE2 + 0x0080,
-
-	EXYNOS5_GPD1 = EXYNOS5_GPIO_BASE2 + 0x00a0,
-
-	EXYNOS5_GPY0 = EXYNOS5_GPIO_BASE2 + 0x00c0,
-	EXYNOS5_GPY1 = EXYNOS5_GPIO_BASE2 + 0x00e0,
-	EXYNOS5_GPY2 = EXYNOS5_GPIO_BASE2 + 0x0100,
-	EXYNOS5_GPY3 = EXYNOS5_GPIO_BASE2 + 0x0120,
-	EXYNOS5_GPY4 = EXYNOS5_GPIO_BASE2 + 0x0140,
-	EXYNOS5_GPY5 = EXYNOS5_GPIO_BASE2 + 0x0160,
-	EXYNOS5_GPY6 = EXYNOS5_GPIO_BASE2 + 0x0180,
-
-	/* base == EXYNOS5_GPIO_BASE3 */
-	EXYNOS5_GPE0 = EXYNOS5_GPIO_BASE3 + 0x0000,
-	EXYNOS5_GPE1 = EXYNOS5_GPIO_BASE3 + 0x0020,
-
-	EXYNOS5_GPF0 = EXYNOS5_GPIO_BASE3 + 0x0040,
-	EXYNOS5_GPF1 = EXYNOS5_GPIO_BASE3 + 0x0060,
-
-	EXYNOS5_GPG0 = EXYNOS5_GPIO_BASE3 + 0x0080,
-	EXYNOS5_GPG1 = EXYNOS5_GPIO_BASE3 + 0x00a0,
-	EXYNOS5_GPG2 = EXYNOS5_GPIO_BASE3 + 0x00c0,
-
-	EXYNOS5_GPJ4 = EXYNOS5_GPIO_BASE3 + 0x00e0,
-
-	/* base == EXYNOS5_GPIO_BASE4 */
-	EXYNOS5_GPA0 = EXYNOS5_GPIO_BASE4 + 0x0000,
-	EXYNOS5_GPA1 = EXYNOS5_GPIO_BASE4 + 0x0020,
-	EXYNOS5_GPA2 = EXYNOS5_GPIO_BASE4 + 0x0040,
-
-	EXYNOS5_GPB0 = EXYNOS5_GPIO_BASE4 + 0x0060,
-	EXYNOS5_GPB1 = EXYNOS5_GPIO_BASE4 + 0x0080,
-	EXYNOS5_GPB2 = EXYNOS5_GPIO_BASE4 + 0x00a0,
-	EXYNOS5_GPB3 = EXYNOS5_GPIO_BASE4 + 0x00c0,
-	EXYNOS5_GPB4 = EXYNOS5_GPIO_BASE4 + 0x00e0,
-
-	EXYNOS5_GPH0 = EXYNOS5_GPIO_BASE4 + 0x0100,
-
-	/* base == EXYNOS5_GPIO_BASE5 */
-	EXYNOS5_GPZ0 = EXYNOS5_GPIO_BASE5 + 0x0000,
+	EXYNOS5_GPY7 = EXYNOS5420_GPIO_PART1_BASE + 0x0000,
+
+	EXYNOS5_GPX0 = EXYNOS5420_GPIO_PART2_BASE + 0x0000,
+	EXYNOS5_GPX1 = EXYNOS5420_GPIO_PART2_BASE + 0x0020,
+	EXYNOS5_GPX2 = EXYNOS5420_GPIO_PART2_BASE + 0x0040,
+	EXYNOS5_GPX3 = EXYNOS5420_GPIO_PART2_BASE + 0x0060,
+
+	EXYNOS5_GPC0 = EXYNOS5420_GPIO_PART3_BASE + 0x0000,
+	EXYNOS5_GPC1 = EXYNOS5420_GPIO_PART3_BASE + 0x0020,
+	EXYNOS5_GPC2 = EXYNOS5420_GPIO_PART3_BASE + 0x0040,
+	EXYNOS5_GPC3 = EXYNOS5420_GPIO_PART3_BASE + 0x0060,
+	EXYNOS5_GPC4 = EXYNOS5420_GPIO_PART3_BASE + 0x0080,
+
+	EXYNOS5_GPD1 = EXYNOS5420_GPIO_PART3_BASE + 0x00a0,
+
+	EXYNOS5_GPY0 = EXYNOS5420_GPIO_PART3_BASE + 0x00c0,
+	EXYNOS5_GPY1 = EXYNOS5420_GPIO_PART3_BASE + 0x00e0,
+	EXYNOS5_GPY2 = EXYNOS5420_GPIO_PART3_BASE + 0x0100,
+	EXYNOS5_GPY3 = EXYNOS5420_GPIO_PART3_BASE + 0x0120,
+	EXYNOS5_GPY4 = EXYNOS5420_GPIO_PART3_BASE + 0x0140,
+	EXYNOS5_GPY5 = EXYNOS5420_GPIO_PART3_BASE + 0x0160,
+	EXYNOS5_GPY6 = EXYNOS5420_GPIO_PART3_BASE + 0x0180,
+
+	EXYNOS5_GPE0 = EXYNOS5420_GPIO_PART4_BASE + 0x0000,
+	EXYNOS5_GPE1 = EXYNOS5420_GPIO_PART4_BASE + 0x0020,
+
+	EXYNOS5_GPF0 = EXYNOS5420_GPIO_PART4_BASE + 0x0040,
+	EXYNOS5_GPF1 = EXYNOS5420_GPIO_PART4_BASE + 0x0060,
+
+	EXYNOS5_GPG0 = EXYNOS5420_GPIO_PART4_BASE + 0x0080,
+	EXYNOS5_GPG1 = EXYNOS5420_GPIO_PART4_BASE + 0x00a0,
+	EXYNOS5_GPG2 = EXYNOS5420_GPIO_PART4_BASE + 0x00c0,
+
+	EXYNOS5_GPJ4 = EXYNOS5420_GPIO_PART4_BASE + 0x00e0,
+
+	/* base == EXYNOS5420_GPIO_PART5_BASE */
+	EXYNOS5_GPA0 = EXYNOS5420_GPIO_PART5_BASE + 0x0000,
+	EXYNOS5_GPA1 = EXYNOS5420_GPIO_PART5_BASE + 0x0020,
+	EXYNOS5_GPA2 = EXYNOS5420_GPIO_PART5_BASE + 0x0040,
+
+	EXYNOS5_GPB0 = EXYNOS5420_GPIO_PART5_BASE + 0x0060,
+	EXYNOS5_GPB1 = EXYNOS5420_GPIO_PART5_BASE + 0x0080,
+	EXYNOS5_GPB2 = EXYNOS5420_GPIO_PART5_BASE + 0x00a0,
+	EXYNOS5_GPB3 = EXYNOS5420_GPIO_PART5_BASE + 0x00c0,
+	EXYNOS5_GPB4 = EXYNOS5420_GPIO_PART5_BASE + 0x00e0,
+
+	EXYNOS5_GPH0 = EXYNOS5420_GPIO_PART5_BASE + 0x0100,
+
+	/* base == EXYNOS5420_GPIO_PART6_BASE */
+	EXYNOS5_GPZ0 = EXYNOS5420_GPIO_PART6_BASE + 0x0000,
 };
 
 enum {
diff --git a/src/cpu/samsung/exynos5420/mct.c b/src/cpu/samsung/exynos5420/mct.c
index 4c5cdd1b20..b02fc6d9fa 100644
--- a/src/cpu/samsung/exynos5420/mct.c
+++ b/src/cpu/samsung/exynos5420/mct.c
@@ -21,84 +21,25 @@
 #include <arch/io.h>
 #include "clk.h"
 
-struct __attribute__((packed)) mct_regs
-{
-	uint32_t mct_cfg;
-	uint8_t reserved0[0xfc];
-	uint32_t g_cnt_l;
-	uint32_t g_cnt_u;
-	uint8_t reserved1[0x8];
-	uint32_t g_cnt_wstat;
-	uint8_t reserved2[0xec];
-	uint32_t g_comp0_l;
-	uint32_t g_comp0_u;
-	uint32_t g_comp0_addr_incr;
-	uint8_t reserved3[0x4];
-	uint32_t g_comp1_l;
-	uint32_t g_comp1_u;
-	uint32_t g_comp1_addr_incr;
-	uint8_t reserved4[0x4];
-	uint32_t g_comp2_l;
-	uint32_t g_comp2_u;
-	uint32_t g_comp2_addr_incr;
-	uint8_t reserved5[0x4];
-	uint32_t g_comp3_l;
-	uint32_t g_comp3_u;
-	uint32_t g_comp3_addr_incr;
-	uint8_t reserved6[0x4];
-	uint32_t g_tcon;
-	uint32_t g_int_cstat;
-	uint32_t g_int_enb;
-	uint32_t g_wstat;
-	uint8_t reserved7[0xb0];
-	uint32_t l0_tcntb;
-	uint32_t l0_tcnto;
-	uint32_t l0_icntb;
-	uint32_t l0_icnto;
-	uint32_t l0_frcntb;
-	uint32_t l0_frcnto;
-	uint8_t reserved8[0x8];
-	uint32_t l0_tcon;
-	uint8_t reserved9[0xc];
-	uint32_t l0_int_cstat;
-	uint32_t l0_int_enb;
-	uint8_t reserved10[0x8];
-	uint32_t l0_wstat;
-	uint8_t reserved11[0xbc];
-	uint32_t l1_tcntb;
-	uint32_t l1_tcnto;
-	uint32_t l1_icntb;
-	uint32_t l1_icnto;
-	uint32_t l1_frcntb;
-	uint32_t l1_frcnto;
-	uint8_t reserved12[0x8];
-	uint32_t l1_tcon;
-	uint8_t reserved13[0xc];
-	uint32_t l1_int_cstat;
-	uint32_t l1_int_enb;
-	uint8_t reserved14[0x8];
-	uint32_t l1_wstat;
-};
-
 static int enabled = 0;
-static struct mct_regs *const mct =
-	(struct mct_regs *)MCT_ADDRESS;
 
 uint64_t mct_raw_value(void)
 {
 	if (!enabled) {
-		writel(readl(&mct->g_tcon) | (0x1 << 8), &mct->g_tcon);
+		writel(readl(&exynos_mct->g_tcon) | (0x1 << 8),
+			&exynos_mct->g_tcon);
 		enabled = 1;
 	}
 
-	uint64_t upper = readl(&mct->g_cnt_u);
-	uint64_t lower = readl(&mct->g_cnt_l);
+	uint64_t upper = readl(&exynos_mct->g_cnt_u);
+	uint64_t lower = readl(&exynos_mct->g_cnt_l);
 
 	return (upper << 32) | lower;
 }
 
 void mct_start(void)
 {
-	writel(readl(&mct->g_tcon) | (0x1 << 8), &mct->g_tcon);
+	writel(readl(&exynos_mct->g_tcon) | (0x1 << 8),
+		&exynos_mct->g_tcon);
 	enabled = 1;
 }
diff --git a/src/cpu/samsung/exynos5420/pinmux.c b/src/cpu/samsung/exynos5420/pinmux.c
index 7843487a12..43a4332503 100644
--- a/src/cpu/samsung/exynos5420/pinmux.c
+++ b/src/cpu/samsung/exynos5420/pinmux.c
@@ -21,7 +21,6 @@
 #include <assert.h>
 #include <stdlib.h>
 #include "gpio.h"
-#include "cpu.h"
 #include "pinmux.h"
 
 static void exynos_pinmux_uart(int start, int count)
diff --git a/src/cpu/samsung/exynos5420/power.c b/src/cpu/samsung/exynos5420/power.c
index 8496d8f3d9..f649006f95 100644
--- a/src/cpu/samsung/exynos5420/power.c
+++ b/src/cpu/samsung/exynos5420/power.c
@@ -19,77 +19,58 @@
 
 /* Power setup code for EXYNOS5 */
 
-#include <console/console.h>
 #include <arch/io.h>
 #include <arch/hlt.h>
-#include "cpu.h"
+#include <console/console.h>
 #include "dmc.h"
 #include "power.h"
 #include "setup.h"
 
 void ps_hold_setup(void)
 {
-	struct exynos5_power *power =
-		samsung_get_base_power();
-
 	/* Set PS-Hold high */
-	setbits_le32(&power->ps_hold_ctrl, POWER_PS_HOLD_CONTROL_DATA_HIGH);
+	setbits_le32(&exynos_power->ps_hold_ctrl,
+		     POWER_PS_HOLD_CONTROL_DATA_HIGH);
 }
 
 void power_reset(void)
 {
-	struct exynos5_power *power =
-		samsung_get_base_power();
-
 	/* Clear inform1 so there's no change we think we've got a wake reset */
-	power->inform1 = 0;
+	exynos_power->inform1 = 0;
 
-	setbits_le32(&power->sw_reset, 1);
+	setbits_le32(&exynos_power->sw_reset, 1);
 }
 
 /* This function never returns */
 void power_shutdown(void)
 {
-	struct exynos5_power *power =
-		samsung_get_base_power();
-
-	clrbits_le32(&power->ps_hold_ctrl, POWER_PS_HOLD_CONTROL_DATA_HIGH);
+	clrbits_le32(&exynos_power->ps_hold_ctrl,
+		     POWER_PS_HOLD_CONTROL_DATA_HIGH);
 
 	hlt();
 }
 
 void power_enable_dp_phy(void)
 {
-	struct exynos5_power *power =
-		samsung_get_base_power();
-
-	setbits_le32(&power->dptx_phy_control, EXYNOS_DP_PHY_ENABLE);
+	setbits_le32(&exynos_power->dptx_phy_control, EXYNOS_DP_PHY_ENABLE);
 }
 
 void power_enable_hw_thermal_trip(void)
 {
-	struct exynos5_power *power =
-		samsung_get_base_power();
-
 	/* Enable HW thermal trip */
-	setbits_le32(&power->ps_hold_ctrl, POWER_ENABLE_HW_TRIP);
+	setbits_le32(&exynos_power->ps_hold_ctrl, POWER_ENABLE_HW_TRIP);
 }
 
 uint32_t power_read_reset_status(void)
 {
-	struct exynos5_power *power =
-		samsung_get_base_power();
-
-	return power->inform1;
+	return exynos_power->inform1;
 }
 
 void power_exit_wakeup(void)
 {
-	struct exynos5_power *power =
-		samsung_get_base_power();
 	typedef void (*resume_func)(void);
 
-	((resume_func)power->inform0)();
+	((resume_func)exynos_power->inform0)();
 }
 
 int power_init(void)
@@ -100,10 +81,7 @@ int power_init(void)
 
 void power_enable_xclkout(void)
 {
-	struct exynos5_power *power =
-		samsung_get_base_power();
-
 	/* use xxti for xclk out */
-	clrsetbits_le32(&power->pmu_debug, PMU_DEBUG_CLKOUT_SEL_MASK,
-				PMU_DEBUG_XXTI);
+	clrsetbits_le32(&exynos_power->pmu_debug, PMU_DEBUG_CLKOUT_SEL_MASK,
+			PMU_DEBUG_XXTI);
 }
diff --git a/src/cpu/samsung/exynos5420/power.h b/src/cpu/samsung/exynos5420/power.h
index 29d3d14a10..e65c4bd976 100644
--- a/src/cpu/samsung/exynos5420/power.h
+++ b/src/cpu/samsung/exynos5420/power.h
@@ -22,6 +22,8 @@
 #ifndef CPU_SAMSUNG_EXYNOS5420_POWER_H
 #define CPU_SAMSUNG_EXYNOS5420_POWER_H
 
+#include "cpu.h"
+
 /* Enable HW thermal trip with PS_HOLD_CONTROL register ENABLE_HW_TRIP bit */
 void power_enable_hw_thermal_trip(void);
 
@@ -54,12 +56,26 @@ struct exynos5_power {
 	uint8_t		reserved5[0xdc];
 	uint32_t	inform0;		/* 0x0800 */
 	uint32_t	inform1;		/* 0x0804 */
-	uint8_t		reserved6[0x1f8];
-	uint32_t	pmu_debug;		/* 0x0A00*/
-	uint8_t         reserved7[0x2908];
+	uint8_t		reserved6[0x0f8];
+	uint32_t	spare0;			/* 0x0900 */
+	uint8_t		reserved7[0x0fc];
+	uint32_t	pmu_debug;		/* 0x0a00 */
+	uint8_t         reserved8[0x15fc];
+	struct {				/* 0x2000 */
+		uint32_t	config;		/*   0x00 */
+		uint32_t	status;		/*   0x04 */
+		uint8_t		reserved[0x78];
+	} arm_core[4];
+	uint8_t		reserved9[0xe04];
+	uint32_t	padret_dram_status;	/* 0x3004 */
+	uint8_t         reservedA[0x1e0];
+	uint32_t	padret_dram_cblk_opt;	/* 0x31e8 */
+	uint8_t         reservedB[0x120];
 	uint32_t	ps_hold_ctrl;		/* 0x330c */
 } __attribute__ ((__packed__));
 
+static struct exynos5_power * const exynos_power = (void*)EXYNOS5_POWER_BASE;
+
 /**
  * Perform a software reset.
  */
diff --git a/src/cpu/samsung/exynos5420/smp.c b/src/cpu/samsung/exynos5420/smp.c
index 069110c069..6fc2fb01ea 100644
--- a/src/cpu/samsung/exynos5420/smp.c
+++ b/src/cpu/samsung/exynos5420/smp.c
@@ -18,14 +18,14 @@
  * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
  */
 
+#include <stdlib.h>
+#include <string.h>
 #include <types.h>
 #include <arch/cpu.h>
 #include <arch/io.h>
-#include <stdlib.h>
-#include <string.h>
 
-#include <cpu/samsung/exynos5420/cpu.h>
-#include <cpu/samsung/exynos5420/power.h>
+#include "cpu.h"
+#include "power.h"
 
 /* ACTLR, L2CTLR L2ACTLR constants used in SMP core power up. */
 
@@ -153,7 +153,7 @@ static void enable_smp(void)
 	actlr |= ACTLR_SMP;
 
 	/* Dummy read to assure L2 access */
-	val = readl((void*)INF_REG_BASE);
+	val = readl(&exynos_power->inform0);
 	val &= 0;
 	actlr |= val;
 
@@ -166,7 +166,6 @@ static void enable_smp(void)
 static void core_start_execution(void)
 {
 	u32 cpu_id, cpu_state;
-	struct exynos5_power *power = samsung_get_base_power();
 
 	enable_smp();
 	set_system_mode();
@@ -180,9 +179,9 @@ static void core_start_execution(void)
 	}
 
 	/* Standard Exynos suspend/resume. */
-	if (power->inform1) {
-		power->inform1 = 0;
-		jump_bx((void*)power->inform0);
+	if (exynos_power->inform1) {
+		exynos_power->inform1 = 0;
+		jump_bx((void*)exynos_power->inform0);
 		/* never returns. */
 	}
 
@@ -202,7 +201,7 @@ static void low_power_start(void)
 	/* On warm reset, because iRAM is not cleared, all cores will enter
 	 * low_power_start, not the initial address. So we need to check reset
 	 * status again, and jump to 0x0 in that case. */
-	reg_val = readl((void*)RST_FLAG_REG);
+	reg_val = readl(&exynos_power->spare0);
 	if (reg_val != RST_FLAG_VAL) {
 		writel(0x0, VECTOR_LOW_POWER_FLAG);
 		jump_bx(CORE_RESET_INIT_ADDRESS);
@@ -260,7 +259,7 @@ static void power_down_core(void)
 	 * S5E5420A User Manual, 8.8.1.202, ARM_CORE0_CONFIGURATION, two bits to
 	 * control power state in each power down level.
 	 */
-	writel(0x0, (void*)(ARM_CORE0_CONFIG + core_id * CORE_CONFIG_OFFSET));
+	writel(0x0, &exynos_power->arm_core[core_id].config);
 
 	/* S5E5420A User Manual, 8.4.2.5, after ARM_CORE*_CONFIGURATION has been
 	 * set to zero, PMU will detect and wait for WFI then run power-down
@@ -288,7 +287,7 @@ static void configure_secondary_cores(void)
 	/* set low_power flag and address */
 	writel((intptr_t)low_power_start, VECTOR_LOW_POWER_ADDRESS);
 	writel(RST_FLAG_VAL, VECTOR_LOW_POWER_FLAG);
-	writel(RST_FLAG_VAL, (void*)RST_FLAG_REG);
+	writel(RST_FLAG_VAL, &exynos_power->spare0);
 
 	/* On next SEV, shutdown all cores. */
 	writel((intptr_t)power_down_core, VECTOR_CORE_SEV_HANDLER);
diff --git a/src/cpu/samsung/exynos5420/spi.c b/src/cpu/samsung/exynos5420/spi.c
index 0d2d6d7fd9..c6c08e925c 100644
--- a/src/cpu/samsung/exynos5420/spi.c
+++ b/src/cpu/samsung/exynos5420/spi.c
@@ -49,12 +49,12 @@ static struct exynos_spi_slave exynos_spi_slaves[3] = {
 	// SPI 0
 	{
 		.slave = { .bus = 0, },
-		.regs = samsung_get_base_spi0(),
+		.regs = (void *)EXYNOS5_SPI0_BASE,
 	},
 	// SPI 1
 	{
 		.slave = { .bus = 1, .rw = SPI_READ_FLAG, },
-		.regs = samsung_get_base_spi1(),
+		.regs = (void *)EXYNOS5_SPI1_BASE,
 		.fifo_size = 64,
 		.half_duplex = 0,
 	},
@@ -62,7 +62,7 @@ static struct exynos_spi_slave exynos_spi_slaves[3] = {
 	{
 		.slave = { .bus = 2,
 			   .rw = SPI_READ_FLAG | SPI_WRITE_FLAG, },
-		.regs = samsung_get_base_spi2(),
+		.regs = (void *)EXYNOS5_SPI2_BASE,
 		.fifo_size = 64,
 		.half_duplex = 1,
 		.frame_header = 0xec,
diff --git a/src/cpu/samsung/exynos5420/sysreg.h b/src/cpu/samsung/exynos5420/sysreg.h
index 3af95d286b..fa25def318 100644
--- a/src/cpu/samsung/exynos5420/sysreg.h
+++ b/src/cpu/samsung/exynos5420/sysreg.h
@@ -22,6 +22,8 @@
 #ifndef CPU_SAMSUNG_EXYNOS5420_SYSREG_H
 #define CPU_SAMSUNG_EXYNOS5420_SYSREG_H
 
+#include "cpu.h"
+
 /* sysreg map */
 struct exynos5_sysreg {
 	/* Add registers as and when required */
@@ -31,6 +33,9 @@ struct exynos5_sysreg {
 	unsigned int	usb20_phy_cfg;
 };
 
+static struct exynos5_sysreg * const exynos_sysreg =
+		(void *)EXYNOS5_SYSREG_BASE;
+
 #define FIMDBYPASS_DISP1	(1 << 15)
 #define USB20_PHY_CFG_EN	(1 << 0)
 
diff --git a/src/cpu/samsung/exynos5420/uart.c b/src/cpu/samsung/exynos5420/uart.c
index 8fd4dea61f..be96d5b86c 100644
--- a/src/cpu/samsung/exynos5420/uart.c
+++ b/src/cpu/samsung/exynos5420/uart.c
@@ -17,6 +17,7 @@
  * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
  */
 
+#include <types.h>
 #include <console/uart.h>
 #include <arch/io.h>
 #include <boot/coreboot_tables.h>
@@ -24,6 +25,7 @@
 #include "clk.h"
 #include "cpu.h"
 #include "periph.h"
+#include "uart.h"
 
 #define RX_FIFO_COUNT_MASK	0xff
 #define RX_FIFO_FULL_MASK	(1 << 8)
diff --git a/src/cpu/samsung/exynos5420/uart.h b/src/cpu/samsung/exynos5420/uart.h
index dcf9ed7aea..72a5789b6d 100644
--- a/src/cpu/samsung/exynos5420/uart.h
+++ b/src/cpu/samsung/exynos5420/uart.h
@@ -21,12 +21,6 @@
 #ifndef CPU_SAMSUNG_EXYNOS5420_UART_H
 #define CPU_SAMSUNG_EXYNOS5420_UART_H
 
-#define EXYNOS5_UART0_BASE	0x12c00000
-#define EXYNOS5_UART1_BASE	0x12c10000
-#define EXYNOS5_UART2_BASE	0x12c20000
-#define EXYNOS5_UART3_BASE	0x12c30000
-#define EXYNOS5_ISP_UART_BASE	0x13190000
-
 /* baudrate rest value */
 union br_rest {
 	unsigned short	slot;		/* udivslot */
diff --git a/src/cpu/samsung/exynos5420/usb.c b/src/cpu/samsung/exynos5420/usb.c
index 9e990a1137..521ea4da5a 100644
--- a/src/cpu/samsung/exynos5420/usb.c
+++ b/src/cpu/samsung/exynos5420/usb.c
@@ -22,7 +22,6 @@
 #include <arch/io.h>
 #include <console/console.h>
 #include <device/device.h>
-#include "cpu.h"
 #include "gpio.h"
 #include "power.h"
 #include "sysreg.h"
@@ -31,17 +30,15 @@
 void setup_usb_host_phy(int hsic_gpio)
 {
 	unsigned int hostphy_ctrl0;
-	struct exynos5_sysreg *sysreg = samsung_get_base_sysreg();
-	struct exynos5_power *power = samsung_get_base_power();
-	struct exynos5_usb_host_phy *phy = samsung_get_base_usb_host_phy();
 
-	setbits_le32(&sysreg->usb20_phy_cfg, USB20_PHY_CFG_EN);
-	setbits_le32(&power->usb_host_phy_ctrl, POWER_USB_HOST_PHY_CTRL_EN);
+	setbits_le32(&exynos_sysreg->usb20_phy_cfg, USB20_PHY_CFG_EN);
+	setbits_le32(&exynos_power->usb_host_phy_ctrl,
+		     POWER_USB_HOST_PHY_CTRL_EN);
 
 	printk(BIOS_DEBUG, "Powering up USB HOST PHY (%s HSIC)\n",
 			hsic_gpio ? "with" : "without");
 
-	hostphy_ctrl0 = readl(&phy->usbphyctrl0);
+	hostphy_ctrl0 = readl(&exynos_usb_host_phy->usbphyctrl0);
 	hostphy_ctrl0 &= ~(HOST_CTRL0_FSEL_MASK |
 			   HOST_CTRL0_COMMONON_N |
 			   /* HOST Phy setting */
@@ -55,15 +52,15 @@ void setup_usb_host_phy(int hsic_gpio)
 			  /* HOST Phy setting */
 			  HOST_CTRL0_LINKSWRST |
 			  HOST_CTRL0_UTMISWRST);
-	writel(hostphy_ctrl0, &phy->usbphyctrl0);
+	writel(hostphy_ctrl0, &exynos_usb_host_phy->usbphyctrl0);
 	udelay(10);
-	clrbits_le32(&phy->usbphyctrl0,
+	clrbits_le32(&exynos_usb_host_phy->usbphyctrl0,
 		     HOST_CTRL0_LINKSWRST |
 		     HOST_CTRL0_UTMISWRST);
 	udelay(20);
 
 	/* EHCI Ctrl setting */
-	setbits_le32(&phy->ehcictrl,
+	setbits_le32(&exynos_usb_host_phy->ehcictrl,
 		     EHCICTRL_ENAINCRXALIGN |
 		     EHCICTRL_ENAINCR4 |
 		     EHCICTRL_ENAINCR8 |
@@ -76,13 +73,15 @@ void setup_usb_host_phy(int hsic_gpio)
 		gpio_direction_output(hsic_gpio, 1);
 		udelay(5000);
 
-		clrbits_le32(&phy->hsicphyctrl1,
+		clrbits_le32(&exynos_usb_host_phy->hsicphyctrl1,
 			     HOST_CTRL0_SIDDQ |
 			     HOST_CTRL0_FORCESLEEP |
 			     HOST_CTRL0_FORCESUSPEND);
-		setbits_le32(&phy->hsicphyctrl1, HOST_CTRL0_PHYSWRST);
+		setbits_le32(&exynos_usb_host_phy->hsicphyctrl1,
+			     HOST_CTRL0_PHYSWRST);
 		udelay(10);
-		clrbits_le32(&phy->hsicphyctrl1, HOST_CTRL0_PHYSWRST);
+		clrbits_le32(&exynos_usb_host_phy->hsicphyctrl1,
+			     HOST_CTRL0_PHYSWRST);
 	}
 
 	/* At this point we need to wait for 50ms before talking to
diff --git a/src/cpu/samsung/exynos5420/usb.h b/src/cpu/samsung/exynos5420/usb.h
index 7837eb2f80..7eb317c68e 100644
--- a/src/cpu/samsung/exynos5420/usb.h
+++ b/src/cpu/samsung/exynos5420/usb.h
@@ -20,6 +20,8 @@
 #ifndef CPU_SAMSUNG_EXYNOS5420_USB_H
 #define CPU_SAMSUNG_EXYNOS5420_USB_H
 
+#include "cpu.h"
+
 #define CLK_24MHZ               5
 
 #define HOST_CTRL0_PHYSWRSTALL                  (1 << 31)
@@ -57,6 +59,9 @@ struct exynos5_usb_host_phy {
         uint32_t usbotgtune;
 };
 
+static struct exynos5_usb_host_phy * const exynos_usb_host_phy =
+		(void *)EXYNOS5_USB_HOST_PHY_BASE;
+
 /* Leave hsic_gpio at 0 to not enable HSIC. */
 void setup_usb_host_phy(int hsic_gpio);