summaryrefslogtreecommitdiff
path: root/src/cpu/samsung/exynos5420
diff options
context:
space:
mode:
authorGabe Black <gabeblack@google.com>2013-05-17 11:29:22 -0700
committerStefan Reinauer <stefan.reinauer@coreboot.org>2013-07-10 21:43:24 +0200
commit5420e0913144e3abbd0f36dbfbc0bcbe8f052e7b (patch)
tree3dec30e8c9506ec81f308b5f9b419b16d38303c6 /src/cpu/samsung/exynos5420
parent99ed2a83b5ae69d134333deaa7d326b9c0aa08b7 (diff)
exynos5420: Replace the 5250 clock logic with 5420.
The new code is stolen from U-Boot with little or no understanding of how it works. Change-Id: I3de7d25174072f6068d9d4fdaa308c0462296737 Signed-off-by: Gabe Black <gabeblack@chromium.org> Reviewed-on: http://review.coreboot.org/3658 Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
Diffstat (limited to 'src/cpu/samsung/exynos5420')
-rw-r--r--src/cpu/samsung/exynos5420/clk.h1213
-rw-r--r--src/cpu/samsung/exynos5420/clock.c198
-rw-r--r--src/cpu/samsung/exynos5420/clock_init.c491
-rw-r--r--src/cpu/samsung/exynos5420/setup.h393
4 files changed, 1208 insertions, 1087 deletions
diff --git a/src/cpu/samsung/exynos5420/clk.h b/src/cpu/samsung/exynos5420/clk.h
index 631b637e4c..b98a67384b 100644
--- a/src/cpu/samsung/exynos5420/clk.h
+++ b/src/cpu/samsung/exynos5420/clk.h
@@ -31,11 +31,13 @@ enum periph_id;
#define HPLL 3
#define VPLL 4
#define BPLL 5
+#define RPLL 6
+#define SPLL 7
enum pll_src_bit {
- SRC_MPLL = 6,
- SRC_EPLL,
- SRC_VPLL,
+ EXYNOS_SRC_MPLL = 6,
+ EXYNOS_SRC_EPLL,
+ EXYNOS_SRC_VPLL,
};
/* *
@@ -106,360 +108,854 @@ void clock_select_i2s_clk_source(void);
int clock_set_i2s_clk_prescaler(unsigned int src_frq, unsigned int dst_frq);
struct exynos5_clock {
- unsigned int apll_lock; /* base + 0 */
- unsigned char res1[0xfc];
- unsigned int apll_con0;
- unsigned int apll_con1;
- unsigned char res2[0xf8];
- unsigned int src_cpu;
- unsigned char res3[0x1fc];
- unsigned int mux_stat_cpu;
- unsigned char res4[0xfc];
- unsigned int div_cpu0;
- unsigned int div_cpu1;
- unsigned char res5[0xf8];
- unsigned int div_stat_cpu0;
- unsigned int div_stat_cpu1;
- unsigned char res6[0x1f8];
- unsigned int gate_sclk_cpu;
- unsigned char res7[0x1fc];
- unsigned int clkout_cmu_cpu;
- unsigned int clkout_cmu_cpu_div_stat;
- unsigned char res8[0x5f8];
-
- unsigned int armclk_stopctrl; /* base + 0x1000 */
- unsigned int atclk_stopctrl;
- unsigned char res9[0x8];
- unsigned int parityfail_status;
- unsigned int parityfail_clear;
- unsigned char res10[0x8];
- unsigned int pwr_ctrl;
- unsigned int pwr_ctr2;
- unsigned char res11[0xd8];
- unsigned int apll_con0_l8;
- unsigned int apll_con0_l7;
- unsigned int apll_con0_l6;
- unsigned int apll_con0_l5;
- unsigned int apll_con0_l4;
- unsigned int apll_con0_l3;
- unsigned int apll_con0_l2;
- unsigned int apll_con0_l1;
- unsigned int iem_control;
- unsigned char res12[0xdc];
- unsigned int apll_con1_l8;
- unsigned int apll_con1_l7;
- unsigned int apll_con1_l6;
- unsigned int apll_con1_l5;
- unsigned int apll_con1_l4;
- unsigned int apll_con1_l3;
- unsigned int apll_con1_l2;
- unsigned int apll_con1_l1;
- unsigned char res13[0xe0];
- unsigned int div_iem_l8;
- unsigned int div_iem_l7;
- unsigned int div_iem_l6;
- unsigned int div_iem_l5;
- unsigned int div_iem_l4;
- unsigned int div_iem_l3;
- unsigned int div_iem_l2;
- unsigned int div_iem_l1;
- unsigned char res14[0x2ce0];
-
- unsigned int mpll_lock; /* base + 0x4000 */
- unsigned char res15[0xfc];
- unsigned int mpll_con0;
- unsigned int mpll_con1;
- unsigned char res16[0xf8];
- unsigned int src_core0;
- unsigned int src_core1;
- unsigned char res17[0xf8];
- unsigned int src_mask_core;
- unsigned char res18[0x100];
- unsigned int mux_stat_core1;
- unsigned char res19[0xf8];
- unsigned int div_core0;
- unsigned int div_core1;
- unsigned int div_sysrgt;
- unsigned char res20[0xf4];
- unsigned int div_stat_core0;
- unsigned int div_stat_core1;
- unsigned int div_stat_sysrgt;
- unsigned char res21[0x2f4];
- unsigned int gate_ip_core;
- unsigned int gate_ip_sysrgt;
- unsigned char res22[0xf8];
- unsigned int clkout_cmu_core;
- unsigned int clkout_cmu_core_div_stat;
- unsigned char res23[0x5f8];
-
- unsigned int dcgidx_map0; /* base + 0x5000 */
- unsigned int dcgidx_map1;
- unsigned int dcgidx_map2;
- unsigned char res24[0x14];
- unsigned int dcgperf_map0;
- unsigned int dcgperf_map1;
- unsigned char res25[0x18];
- unsigned int dvcidx_map;
- unsigned char res26[0x1c];
- unsigned int freq_cpu;
- unsigned int freq_dpm;
- unsigned char res27[0x18];
- unsigned int dvsemclk_en;
- unsigned int maxperf;
- unsigned char res28[0x3478];
-
- unsigned int div_acp; /* base + 0x8500 */
- unsigned char res29[0xfc];
- unsigned int div_stat_acp;
- unsigned char res30[0x1fc];
- unsigned int gate_ip_acp;
- unsigned char res31a[0xfc];
- unsigned int div_syslft;
- unsigned char res31b[0xc];
- unsigned int div_stat_syslft;
- unsigned char res31c[0xc];
- unsigned int gate_bus_syslft;
- unsigned char res31d[0xdc];
- unsigned int clkout_cmu_acp;
- unsigned int clkout_cmu_acp_div_stat;
- unsigned char res32[0x38f8];
-
- unsigned int div_isp0; /* base + 0xc300 */
- unsigned int div_isp1;
- unsigned int div_isp2;
- unsigned char res33[0xf4];
-
- unsigned int div_stat_isp0; /* base + 0xc400 */
- unsigned int div_stat_isp1;
- unsigned int div_stat_isp2;
- unsigned char res34[0x3f4];
-
- unsigned int gate_ip_isp0; /* base + 0xc800 */
- unsigned int gate_ip_isp1;
- unsigned char res35[0xf8];
- unsigned int gate_sclk_isp;
- unsigned char res36[0xc];
- unsigned int mcuisp_pwr_ctrl;
- unsigned char res37[0xec];
- unsigned int clkout_cmu_isp;
- unsigned int clkout_cmu_isp_div_stat;
- unsigned char res38[0x3618];
-
- unsigned int cpll_lock; /* base + 0x10020 */
- unsigned char res39[0xc];
- unsigned int epll_lock;
- unsigned char res40[0xc];
- unsigned int vpll_lock;
- unsigned char res41a[0xc];
- unsigned int gpll_lock;
- unsigned char res41b[0xcc];
- unsigned int cpll_con0;
- unsigned int cpll_con1;
- unsigned char res42[0x8];
- unsigned int epll_con0;
- unsigned int epll_con1;
- unsigned int epll_con2;
- unsigned char res43[0x4];
- unsigned int vpll_con0;
- unsigned int vpll_con1;
- unsigned int vpll_con2;
- unsigned char res44a[0x4];
- unsigned int gpll_con0;
- unsigned int gpll_con1;
- unsigned char res44b[0xb8];
- unsigned int src_top0;
- unsigned int src_top1;
- unsigned int src_top2;
- unsigned int src_top3;
- unsigned int src_gscl;
- unsigned int src_disp0_0;
- unsigned int src_disp0_1;
- unsigned int src_disp1_0;
- unsigned int src_disp1_1;
- unsigned char res46[0xc];
- unsigned int src_mau;
- unsigned int src_fsys;
- unsigned char res47[0x8];
- unsigned int src_peric0;
- unsigned int src_peric1;
- unsigned char res48[0x18];
- unsigned int sclk_src_isp;
- unsigned char res49[0x9c];
- unsigned int src_mask_top;
- unsigned char res50[0xc];
- unsigned int src_mask_gscl;
- unsigned int src_mask_disp0_0;
- unsigned int src_mask_disp0_1;
- unsigned int src_mask_disp1_0;
- unsigned int src_mask_disp1_1;
- unsigned int src_mask_maudio;
- unsigned char res52[0x8];
- unsigned int src_mask_fsys;
- unsigned char res53[0xc];
- unsigned int src_mask_peric0;
- unsigned int src_mask_peric1;
- unsigned char res54[0x18];
- unsigned int src_mask_isp;
- unsigned char res55[0x9c];
- unsigned int mux_stat_top0;
- unsigned int mux_stat_top1;
- unsigned int mux_stat_top2;
- unsigned int mux_stat_top3;
- unsigned char res56[0xf0];
- unsigned int div_top0;
- unsigned int div_top1;
- unsigned char res57[0x8];
- unsigned int div_gscl;
- unsigned int div_disp0_0;
- unsigned int div_disp0_1;
- unsigned int div_disp1_0;
- unsigned int div_disp1_1;
- unsigned char res59[0x8];
- unsigned int div_gen;
- unsigned char res60[0x4];
- unsigned int div_mau;
- unsigned int div_fsys0;
- unsigned int div_fsys1;
- unsigned int div_fsys2;
- unsigned int div_fsys3;
- unsigned int div_peric0;
- unsigned int div_peric1;
- unsigned int div_peric2;
- unsigned int div_peric3;
- unsigned int div_peric4;
- unsigned int div_peric5;
- unsigned char res61[0x10];
- unsigned int sclk_div_isp;
- unsigned char res62[0xc];
- unsigned int div2_ratio0;
- unsigned int div2_ratio1;
- unsigned char res63[0x8];
- unsigned int div4_ratio;
- unsigned char res64[0x6c];
- unsigned int div_stat_top0;
- unsigned int div_stat_top1;
- unsigned char res65[0x8];
- unsigned int div_stat_gscl;
- unsigned int div_stat_disp0_0;
- unsigned int div_stat_disp0_1;
- unsigned int div_stat_disp1_0;
- unsigned int div_stat_disp1_1;
- unsigned char res67[0x8];
- unsigned int div_stat_gen;
- unsigned char res68[0x4];
- unsigned int div_stat_maudio;
- unsigned int div_stat_fsys0;
- unsigned int div_stat_fsys1;
- unsigned int div_stat_fsys2;
- unsigned int div_stat_fsys3;
- unsigned int div_stat_peric0;
- unsigned int div_stat_peric1;
- unsigned int div_stat_peric2;
- unsigned int div_stat_peric3;
- unsigned int div_stat_peric4;
- unsigned int div_stat_peric5;
- unsigned char res69[0x10];
- unsigned int sclk_div_stat_isp;
- unsigned char res70[0xc];
- unsigned int div2_stat0;
- unsigned int div2_stat1;
- unsigned char res71[0x8];
- unsigned int div4_stat;
- unsigned char res72[0x180];
- unsigned int gate_top_sclk_disp0;
- unsigned int gate_top_sclk_disp1;
- unsigned int gate_top_sclk_gen;
- unsigned char res74[0xc];
- unsigned int gate_top_sclk_mau;
- unsigned int gate_top_sclk_fsys;
- unsigned char res75[0xc];
- unsigned int gate_top_sclk_peric;
- unsigned char res76[0x1c];
- unsigned int gate_top_sclk_isp;
- unsigned char res77[0xac];
- unsigned int gate_ip_gscl;
- unsigned int gate_ip_disp0;
- unsigned int gate_ip_disp1;
- unsigned int gate_ip_mfc;
- unsigned int gate_ip_g3d;
- unsigned int gate_ip_gen;
- unsigned char res79[0xc];
- unsigned int gate_ip_fsys;
- unsigned char res80[0x4];
- unsigned int gate_ip_gps;
- unsigned int gate_ip_peric;
- unsigned char res81[0xc];
- unsigned int gate_ip_peris;
- unsigned char res82[0x1c];
- unsigned int gate_block;
- unsigned char res83[0x7c];
- unsigned int clkout_cmu_top;
- unsigned int clkout_cmu_top_div_stat;
- unsigned char res84[0x37f8];
-
- unsigned int src_lex; /* base + 0x14200 */
- unsigned char res85[0x1fc];
- unsigned int mux_stat_lex;
- unsigned char res85b[0xfc];
- unsigned int div_lex;
- unsigned char res86[0xfc];
- unsigned int div_stat_lex;
- unsigned char res87[0x1fc];
- unsigned int gate_ip_lex;
- unsigned char res88[0x1fc];
- unsigned int clkout_cmu_lex;
- unsigned int clkout_cmu_lex_div_stat;
- unsigned char res89[0x3af8];
-
- unsigned int div_r0x; /* base + 0x18500 */
- unsigned char res90[0xfc];
- unsigned int div_stat_r0x;
- unsigned char res91[0x1fc];
- unsigned int gate_ip_r0x;
- unsigned char res92[0x1fc];
- unsigned int clkout_cmu_r0x;
- unsigned int clkout_cmu_r0x_div_stat;
- unsigned char res94[0x3af8];
-
- unsigned int div_r1x; /* base + 0x1c500 */
- unsigned char res95[0xfc];
- unsigned int div_stat_r1x;
- unsigned char res96[0x1fc];
- unsigned int gate_ip_r1x;
- unsigned char res97[0x1fc];
- unsigned int clkout_cmu_r1x;
- unsigned int clkout_cmu_r1x_div_stat;
- unsigned char res98[0x3608];
-
- unsigned int bpll_lock; /* base + 0x2000c */
- unsigned char res99[0xfc];
- unsigned int bpll_con0;
- unsigned int bpll_con1;
- unsigned char res100[0xe8];
- unsigned int src_cdrex;
- unsigned char res101[0x1fc];
- unsigned int mux_stat_cdrex;
- unsigned char res102[0xfc];
- unsigned int div_cdrex;
- unsigned int div_cdrex2;
- unsigned char res103[0xf8];
- unsigned int div_stat_cdrex;
- unsigned char res104[0x2fc];
- unsigned int gate_ip_cdrex;
- unsigned char res105[0xc];
- unsigned int c2c_monitor;
- unsigned int dmc_pwr_ctrl;
- unsigned char res106[0x4];
- unsigned int drex2_pause;
- unsigned char res107[0xe0];
- unsigned int clkout_cmu_cdrex;
- unsigned int clkout_cmu_cdrex_div_stat;
- unsigned char res108[0x8];
- unsigned int lpddr3phy_ctrl;
- unsigned char res109a[0xc];
- unsigned int lpddr3phy_con3;
- unsigned int pll_div2_sel;
- unsigned char res109b[0xf5e4];
+ uint32_t apll_lock; /* base + 0 */
+ uint8_t res1[0xfc];
+ uint32_t apll_con0;
+ uint32_t apll_con1;
+ uint8_t res2[0xf8];
+ uint32_t src_cpu;
+ uint8_t res3[0x1fc];
+ uint32_t mux_stat_cpu;
+ uint8_t res4[0xfc];
+ uint32_t div_cpu0;
+ uint32_t div_cpu1;
+ uint8_t res5[0xf8];
+ uint32_t div_stat_cpu0;
+ uint32_t div_stat_cpu1;
+ uint8_t res6[0x1f8];
+ uint32_t gate_sclk_cpu;
+ uint8_t res7[0x1fc];
+ uint32_t clkout_cmu_cpu;
+ uint32_t clkout_cmu_cpu_div_stat;
+ uint8_t res8[0x5f8];
+
+ uint32_t armclk_stopctrl; /* base + 0x1000 */
+ uint32_t atclk_stopctrl;
+ uint8_t res9[0x8];
+ uint32_t parityfail_status;
+ uint32_t parityfail_clear;
+ uint8_t res10[0x8];
+ uint32_t pwr_ctrl;
+ uint32_t pwr_ctr2;
+ uint8_t res11[0xd8];
+ uint32_t apll_con0_l8;
+ uint32_t apll_con0_l7;
+ uint32_t apll_con0_l6;
+ uint32_t apll_con0_l5;
+ uint32_t apll_con0_l4;
+ uint32_t apll_con0_l3;
+ uint32_t apll_con0_l2;
+ uint32_t apll_con0_l1;
+ uint32_t iem_control;
+ uint8_t res12[0xdc];
+ uint32_t apll_con1_l8;
+ uint32_t apll_con1_l7;
+ uint32_t apll_con1_l6;
+ uint32_t apll_con1_l5;
+ uint32_t apll_con1_l4;
+ uint32_t apll_con1_l3;
+ uint32_t apll_con1_l2;
+ uint32_t apll_con1_l1;
+ uint8_t res13[0xe0];
+ uint32_t div_iem_l8;
+ uint32_t div_iem_l7;
+ uint32_t div_iem_l6;
+ uint32_t div_iem_l5;
+ uint32_t div_iem_l4;
+ uint32_t div_iem_l3;
+ uint32_t div_iem_l2;
+ uint32_t div_iem_l1;
+ uint8_t res14[0x2ce0];
+
+ uint32_t mpll_lock; /* base + 0x4000 */
+ uint8_t res15[0xfc];
+ uint32_t mpll_con0;
+ uint32_t mpll_con1;
+ uint8_t res16[0xf8];
+ uint32_t src_core0;
+ uint32_t src_core1;
+ uint8_t res17[0xf8];
+ uint32_t src_mask_core;
+ uint8_t res18[0x100];
+ uint32_t mux_stat_core1;
+ uint8_t res19[0xf8];
+ uint32_t div_core0;
+ uint32_t div_core1;
+ uint32_t div_sysrgt;
+ uint8_t res20[0xf4];
+ uint32_t div_stat_core0;
+ uint32_t div_stat_core1;
+ uint32_t div_stat_sysrgt;
+ uint8_t res21[0x2f4];
+ uint32_t gate_ip_core;
+ uint32_t gate_ip_sysrgt;
+ uint8_t res22[0xf8];
+ uint32_t clkout_cmu_core;
+ uint32_t clkout_cmu_core_div_stat;
+ uint8_t res23[0x5f8];
+
+ uint32_t dcgidx_map0; /* base + 0x5000 */
+ uint32_t dcgidx_map1;
+ uint32_t dcgidx_map2;
+ uint8_t res24[0x14];
+ uint32_t dcgperf_map0;
+ uint32_t dcgperf_map1;
+ uint8_t res25[0x18];
+ uint32_t dvcidx_map;
+ uint8_t res26[0x1c];
+ uint32_t freq_cpu;
+ uint32_t freq_dpm;
+ uint8_t res27[0x18];
+ uint32_t dvsemclk_en;
+ uint32_t maxperf;
+ uint8_t res28[0x3478];
+
+ uint32_t div_acp; /* base + 0x8500 */
+ uint8_t res29[0xfc];
+ uint32_t div_stat_acp;
+ uint8_t res30[0x1fc];
+ uint32_t gate_ip_acp;
+ uint8_t res31a[0xfc];
+ uint32_t div_syslft;
+ uint8_t res31b[0xc];
+ uint32_t div_stat_syslft;
+ uint8_t res31c[0xc];
+ uint32_t gate_bus_syslft;
+ uint8_t res31d[0xdc];
+ uint32_t clkout_cmu_acp;
+ uint32_t clkout_cmu_acp_div_stat;
+ uint8_t res32[0x38f8];
+
+ uint32_t div_isp0; /* base + 0xc300 */
+ uint32_t div_isp1;
+ uint32_t div_isp2;
+ uint8_t res33[0xf4];
+
+ uint32_t div_stat_isp0; /* base + 0xc400 */
+ uint32_t div_stat_isp1;
+ uint32_t div_stat_isp2;
+ uint8_t res34[0x3f4];
+
+ uint32_t gate_ip_isp0; /* base + 0xc800 */
+ uint32_t gate_ip_isp1;
+ uint8_t res35[0xf8];
+ uint32_t gate_sclk_isp;
+ uint8_t res36[0xc];
+ uint32_t mcuisp_pwr_ctrl;
+ uint8_t res37[0xec];
+ uint32_t clkout_cmu_isp;
+ uint32_t clkout_cmu_isp_div_stat;
+ uint8_t res38[0x3618];
+
+ uint32_t cpll_lock; /* base + 0x10020 */
+ uint8_t res39[0xc];
+ uint32_t epll_lock;
+ uint8_t res40[0xc];
+ uint32_t vpll_lock;
+ uint8_t res41a[0xc];
+ uint32_t gpll_lock;
+ uint8_t res41b[0xcc];
+ uint32_t cpll_con0;
+ uint32_t cpll_con1;
+ uint8_t res42[0x8];
+ uint32_t epll_con0;
+ uint32_t epll_con1;
+ uint32_t epll_con2;
+ uint8_t res43[0x4];
+ uint32_t vpll_con0;
+ uint32_t vpll_con1;
+ uint32_t vpll_con2;
+ uint8_t res44a[0x4];
+ uint32_t gpll_con0;
+ uint32_t gpll_con1;
+ uint8_t res44b[0xb8];
+ uint32_t src_top0;
+ uint32_t src_top1;
+ uint32_t src_top2;
+ uint32_t src_top3;
+ uint32_t src_gscl;
+ uint32_t src_disp0_0;
+ uint32_t src_disp0_1;
+ uint32_t src_disp1_0;
+ uint32_t src_disp1_1;
+ uint8_t res46[0xc];
+ uint32_t src_mau;
+ uint32_t src_fsys;
+ uint8_t res47[0x8];
+ uint32_t src_peric0;
+ uint32_t src_peric1;
+ uint8_t res48[0x18];
+ uint32_t sclk_src_isp;
+ uint8_t res49[0x9c];
+ uint32_t src_mask_top;
+ uint8_t res50[0xc];
+ uint32_t src_mask_gscl;
+ uint32_t src_mask_disp0_0;
+ uint32_t src_mask_disp0_1;
+ uint32_t src_mask_disp1_0;
+ uint32_t src_mask_disp1_1;
+ uint32_t src_mask_maudio;
+ uint8_t res52[0x8];
+ uint32_t src_mask_fsys;
+ uint8_t res53[0xc];
+ uint32_t src_mask_peric0;
+ uint32_t src_mask_peric1;
+ uint8_t res54[0x18];
+ uint32_t src_mask_isp;
+ uint8_t res55[0x9c];
+ uint32_t mux_stat_top0;
+ uint32_t mux_stat_top1;
+ uint32_t mux_stat_top2;
+ uint32_t mux_stat_top3;
+ uint8_t res56[0xf0];
+ uint32_t div_top0;
+ uint32_t div_top1;
+ uint8_t res57[0x8];
+ uint32_t div_gscl;
+ uint32_t div_disp0_0;
+ uint32_t div_disp0_1;
+ uint32_t div_disp1_0;
+ uint32_t div_disp1_1;
+ uint8_t res59[0x8];
+ uint32_t div_gen;
+ uint8_t res60[0x4];
+ uint32_t div_mau;
+ uint32_t div_fsys0;
+ uint32_t div_fsys1;
+ uint32_t div_fsys2;
+ uint32_t div_fsys3;
+ uint32_t div_peric0;
+ uint32_t div_peric1;
+ uint32_t div_peric2;
+ uint32_t div_peric3;
+ uint32_t div_peric4;
+ uint32_t div_peric5;
+ uint8_t res61[0x10];
+ uint32_t sclk_div_isp;
+ uint8_t res62[0xc];
+ uint32_t div2_ratio0;
+ uint32_t div2_ratio1;
+ uint8_t res63[0x8];
+ uint32_t div4_ratio;
+ uint8_t res64[0x6c];
+ uint32_t div_stat_top0;
+ uint32_t div_stat_top1;
+ uint8_t res65[0x8];
+ uint32_t div_stat_gscl;
+ uint32_t div_stat_disp0_0;
+ uint32_t div_stat_disp0_1;
+ uint32_t div_stat_disp1_0;
+ uint32_t div_stat_disp1_1;
+ uint8_t res67[0x8];
+ uint32_t div_stat_gen;
+ uint8_t res68[0x4];
+ uint32_t div_stat_maudio;
+ uint32_t div_stat_fsys0;
+ uint32_t div_stat_fsys1;
+ uint32_t div_stat_fsys2;
+ uint32_t div_stat_fsys3;
+ uint32_t div_stat_peric0;
+ uint32_t div_stat_peric1;
+ uint32_t div_stat_peric2;
+ uint32_t div_stat_peric3;
+ uint32_t div_stat_peric4;
+ uint32_t div_stat_peric5;
+ uint8_t res69[0x10];
+ uint32_t sclk_div_stat_isp;
+ uint8_t res70[0xc];
+ uint32_t div2_stat0;
+ uint32_t div2_stat1;
+ uint8_t res71[0x8];
+ uint32_t div4_stat;
+ uint8_t res72[0x180];
+ uint32_t gate_top_sclk_disp0;
+ uint32_t gate_top_sclk_disp1;
+ uint32_t gate_top_sclk_gen;
+ uint8_t res74[0xc];
+ uint32_t gate_top_sclk_mau;
+ uint32_t gate_top_sclk_fsys;
+ uint8_t res75[0xc];
+ uint32_t gate_top_sclk_peric;
+ uint8_t res76[0x1c];
+ uint32_t gate_top_sclk_isp;
+ uint8_t res77[0xac];
+ uint32_t gate_ip_gscl;
+ uint32_t gate_ip_disp0;
+ uint32_t gate_ip_disp1;
+ uint32_t gate_ip_mfc;
+ uint32_t gate_ip_g3d;
+ uint32_t gate_ip_gen;
+ uint8_t res79[0xc];
+ uint32_t gate_ip_fsys;
+ uint8_t res80[0x4];
+ uint32_t gate_ip_gps;
+ uint32_t gate_ip_peric;
+ uint8_t res81[0xc];
+ uint32_t gate_ip_peris;
+ uint8_t res82[0x1c];
+ uint32_t gate_block;
+ uint8_t res83[0x7c];
+ uint32_t clkout_cmu_top;
+ uint32_t clkout_cmu_top_div_stat;
+ uint8_t res84[0x37f8];
+
+ uint32_t src_lex; /* base + 0x14200 */
+ uint8_t res85[0x1fc];
+ uint32_t mux_stat_lex;
+ uint8_t res85b[0xfc];
+ uint32_t div_lex;
+ uint8_t res86[0xfc];
+ uint32_t div_stat_lex;
+ uint8_t res87[0x1fc];
+ uint32_t gate_ip_lex;
+ uint8_t res88[0x1fc];
+ uint32_t clkout_cmu_lex;
+ uint32_t clkout_cmu_lex_div_stat;
+ uint8_t res89[0x3af8];
+
+ uint32_t div_r0x; /* base + 0x18500 */
+ uint8_t res90[0xfc];
+ uint32_t div_stat_r0x;
+ uint8_t res91[0x1fc];
+ uint32_t gate_ip_r0x;
+ uint8_t res92[0x1fc];
+ uint32_t clkout_cmu_r0x;
+ uint32_t clkout_cmu_r0x_div_stat;
+ uint8_t res94[0x3af8];
+
+ uint32_t div_r1x; /* base + 0x1c500 */
+ uint8_t res95[0xfc];
+ uint32_t div_stat_r1x;
+ uint8_t res96[0x1fc];
+ uint32_t gate_ip_r1x;
+ uint8_t res97[0x1fc];
+ uint32_t clkout_cmu_r1x;
+ uint32_t clkout_cmu_r1x_div_stat;
+ uint8_t res98[0x3608];
+
+ uint32_t bpll_lock; /* base + 0x2000c */
+ uint8_t res99[0xfc];
+ uint32_t bpll_con0;
+ uint32_t bpll_con1;
+ uint8_t res100[0xe8];
+ uint32_t src_cdrex;
+ uint8_t res101[0x1fc];
+ uint32_t mux_stat_cdrex;
+ uint8_t res102[0xfc];
+ uint32_t div_cdrex;
+ uint32_t div_cdrex2;
+ uint8_t res103[0xf8];
+ uint32_t div_stat_cdrex;
+ uint8_t res104[0x2fc];
+ uint32_t gate_ip_cdrex;
+ uint8_t res105[0xc];
+ uint32_t c2c_monitor;
+ uint32_t dmc_pwr_ctrl;
+ uint8_t res106[0x4];
+ uint32_t drex2_pause;
+ uint8_t res107[0xe0];
+ uint32_t clkout_cmu_cdrex;
+ uint32_t clkout_cmu_cdrex_div_stat;
+ uint8_t res108[0x8];
+ uint32_t lpddr3phy_ctrl;
+ uint8_t res109a[0xc];
+ uint32_t lpddr3phy_con3;
+ uint32_t pll_div2_sel;
+ uint8_t res109b[0xf5e4];
+};
+
+struct exynos5420_clock {
+ uint32_t apll_lock; /* 0x10010000 */
+ uint8_t res1[0xfc];
+ uint32_t apll_con0;
+ uint32_t apll_con1;
+ uint8_t res2[0xf8];
+ uint32_t clk_src_cpu;
+ uint8_t res3[0x1fc];
+ uint32_t clk_mux_stat_cpu;
+ uint8_t res4[0xfc];
+ uint32_t clk_div_cpu0; /* 0x10010500 */
+ uint32_t clk_div_cpu1;
+ uint8_t res5[0xf8];
+ uint32_t clk_div_stat_cpu0;
+ uint32_t clk_div_stat_cpu1;
+ uint8_t res6[0xf8];
+ uint32_t clk_gate_bus_cpu;
+ uint8_t res7[0xfc];
+ uint32_t clk_gate_sclk_cpu;
+ uint8_t res8[0x1fc];
+ uint32_t clkout_cmu_cpu; /* 0x10010a00 */
+ uint32_t clkout_cmu_cpu_div_stat;
+ uint8_t res9[0x5f8];
+ uint32_t armclk_stopctrl;
+ uint8_t res10[0x4];
+ uint32_t arm_ema_ctrl;
+ uint32_t arm_ema_status;
+ uint8_t res11[0x10];
+ uint32_t pwr_ctrl;
+ uint32_t pwr_ctrl2;
+ uint8_t res12[0xd8];
+ uint32_t apll_con0_l8; /* 0x1001100 */
+ uint32_t apll_con0_l7;
+ uint32_t apll_con0_l6;
+ uint32_t apll_con0_l5;
+ uint32_t apll_con0_l4;
+ uint32_t apll_con0_l3;
+ uint32_t apll_con0_l2;
+ uint32_t apll_con0_l1;
+ uint32_t iem_control;
+ uint8_t res13[0xdc];
+ uint32_t apll_con1_l8; /* 0x10011200 */
+ uint32_t apll_con1_l7;
+ uint32_t apll_con1_l6;
+ uint32_t apll_con1_l5;
+ uint32_t apll_con1_l4;
+ uint32_t apll_con1_l3;
+ uint32_t apll_con1_l2;
+ uint32_t apll_con1_l1;
+ uint8_t res14[0xe0];
+ uint32_t clkdiv_iem_l8;
+ uint32_t clkdiv_iem_l7; /* 0x10011304 */
+ uint32_t clkdiv_iem_l6;
+ uint32_t clkdiv_iem_l5;
+ uint32_t clkdiv_iem_l4;
+ uint32_t clkdiv_iem_l3;
+ uint32_t clkdiv_iem_l2;
+ uint32_t clkdiv_iem_l1;
+ uint8_t res15[0xe0];
+ uint32_t l2_status;
+ uint8_t res16[0x0c];
+ uint32_t cpu_status; /* 0x10011410 */
+ uint8_t res17[0x0c];
+ uint32_t ptm_status;
+ uint8_t res18[0xbdc];
+ uint32_t cmu_cpu_spare0;
+ uint32_t cmu_cpu_spare1;
+ uint32_t cmu_cpu_spare2;
+ uint32_t cmu_cpu_spare3;
+ uint32_t cmu_cpu_spare4;
+ uint8_t res19[0x1fdc];
+ uint32_t cmu_cpu_version;
+ uint8_t res20[0x20c];
+ uint32_t clk_src_cperi0; /* 0x10014200 */
+ uint32_t clk_src_cperi1;
+ uint8_t res21[0xf8];
+ uint32_t clk_src_mask_cperi;
+ uint8_t res22[0x100];
+ uint32_t clk_mux_stat_cperi1;
+ uint8_t res23[0xfc];
+ uint32_t clk_div_cperi1;
+ uint8_t res24[0xfc];
+ uint32_t clk_div_stat_cperi1;
+ uint8_t res25[0xf8];
+ uint32_t clk_gate_bus_cperi0; /* 0x10014700 */
+ uint32_t clk_gate_bus_cperi1;
+ uint8_t res26[0xf8];
+ uint32_t clk_gate_sclk_cperi;
+ uint8_t res27[0xfc];
+ uint32_t clk_gate_ip_cperi;
+ uint8_t res28[0xfc];
+ uint32_t clkout_cmu_cperi;
+ uint32_t clkout_cmu_cperi_div_stat;
+ uint8_t res29[0x5f8];
+ uint32_t dcgidx_map0; /* 0x10015000 */
+ uint32_t dcgidx_map1;
+ uint32_t dcgidx_map2;
+ uint8_t res30[0x14];
+ uint32_t dcgperf_map0;
+ uint32_t dcgperf_map1;
+ uint8_t res31[0x18];
+ uint32_t dvcidx_map;
+ uint8_t res32[0x1c];
+ uint32_t freq_cpu;
+ uint32_t freq_dpm;
+ uint8_t res33[0x18];
+ uint32_t dvsemclk_en; /* 0x10015080 */
+ uint32_t maxperf;
+ uint8_t res34[0x2e78];
+ uint32_t cmu_cperi_spare0;
+ uint32_t cmu_cperi_spare1;
+ uint32_t cmu_cperi_spare2;
+ uint32_t cmu_cperi_spare3;
+ uint32_t cmu_cperi_spare4;
+ uint32_t cmu_cperi_spare5;
+ uint32_t cmu_cperi_spare6;
+ uint32_t cmu_cperi_spare7;
+ uint32_t cmu_cperi_spare8;
+ uint8_t res35[0xcc];
+ uint32_t cmu_cperi_version; /* 0x10017ff0 */
+ uint8_t res36[0x50c];
+ uint32_t clk_div_g2d;
+ uint8_t res37[0xfc];
+ uint32_t clk_div_stat_g2d;
+ uint8_t res38[0xfc];
+ uint32_t clk_gate_bus_g2d;
+ uint8_t res39[0xfc];
+ uint32_t clk_gate_ip_g2d;
+ uint8_t res40[0x1fc];
+ uint32_t clkout_cmu_g2d;
+ uint32_t clkout_cmu_g2d_div_stat;/* 0x10018a04 */
+ uint8_t res41[0xf8];
+ uint32_t cmu_g2d_spare0;
+ uint32_t cmu_g2d_spare1;
+ uint32_t cmu_g2d_spare2;
+ uint32_t cmu_g2d_spare3;
+ uint32_t cmu_g2d_spare4;
+ uint8_t res42[0x34dc];
+ uint32_t cmu_g2d_version;
+ uint8_t res43[0x30c];
+ uint32_t clk_div_cmu_isp0;
+ uint32_t clk_div_cmu_isp1;
+ uint32_t clk_div_isp2; /* 0x1001c308 */
+ uint8_t res44[0xf4];
+ uint32_t clk_div_stat_cmu_isp0;
+ uint32_t clk_div_stat_cmu_isp1;
+ uint32_t clk_div_stat_isp2;
+ uint8_t res45[0x2f4];
+ uint32_t clk_gate_bus_isp0;
+ uint32_t clk_gate_bus_isp1;
+ uint32_t clk_gate_bus_isp2;
+ uint32_t clk_gate_bus_isp3;
+ uint8_t res46[0xf0];
+ uint32_t clk_gate_ip_isp0;
+ uint32_t clk_gate_ip_isp1;
+ uint8_t res47[0xf8];
+ uint32_t clk_gate_sclk_isp;
+ uint8_t res48[0x0c];
+ uint32_t mcuisp_pwr_ctrl; /* 0x1001c910 */
+ uint8_t res49[0x0ec];
+ uint32_t clkout_cmu_isp;
+ uint32_t clkout_cmu_isp_div_stat;
+ uint8_t res50[0xf8];
+ uint32_t cmu_isp_spare0;
+ uint32_t cmu_isp_spare1;
+ uint32_t cmu_isp_spare2;
+ uint32_t cmu_isp_spare3;
+ uint8_t res51[0x34e0];
+ uint32_t cmu_isp_version;
+ uint8_t res52[0x2c];
+ uint32_t cpll_lock; /* 10020020 */
+ uint8_t res53[0xc];
+ uint32_t dpll_lock;
+ uint8_t res54[0xc];
+ uint32_t epll_lock;
+ uint8_t res55[0xc];
+ uint32_t rpll_lock;
+ uint8_t res56[0xc];
+ uint32_t ipll_lock;
+ uint8_t res57[0xc];
+ uint32_t spll_lock;
+ uint8_t res58[0xc];
+ uint32_t vpll_lock;
+ uint8_t res59[0xc];
+ uint32_t mpll_lock;
+ uint8_t res60[0x8c];
+ uint32_t cpll_con0; /* 10020120 */
+ uint32_t cpll_con1;
+ uint32_t dpll_con0;
+ uint32_t dpll_con1;
+ uint32_t epll_con0;
+ uint32_t epll_con1;
+ uint32_t epll_con2;
+ uint8_t res601[0x4];
+ uint32_t rpll_con0;
+ uint32_t rpll_con1;
+ uint32_t rpll_con2;
+ uint8_t res602[0x4];
+ uint32_t ipll_con0;
+ uint32_t ipll_con1;
+ uint8_t res61[0x8];
+ uint32_t spll_con0;
+ uint32_t spll_con1;
+ uint8_t res62[0x8];
+ uint32_t vpll_con0;
+ uint32_t vpll_con1;
+ uint8_t res63[0x8];
+ uint32_t mpll_con0;
+ uint32_t mpll_con1;
+ uint8_t res64[0x78];
+ uint32_t clk_src_top0; /* 0x10020200 */
+ uint32_t clk_src_top1;
+ uint32_t clk_src_top2;
+ uint32_t clk_src_top3;
+ uint32_t clk_src_top4;
+ uint32_t clk_src_top5;
+ uint32_t clk_src_top6;
+ uint32_t clk_src_top7;
+ uint8_t res65[0xc];
+ uint32_t clk_src_disp10; /* 0x1002022c */
+ uint8_t res66[0x10];
+ uint32_t clk_src_mau;
+ uint32_t clk_src_fsys;
+ uint8_t res67[0x8];
+ uint32_t clk_src_peric0;
+ uint32_t clk_src_peric1;
+ uint8_t res68[0x18];
+ uint32_t clk_src_isp;
+ uint8_t res69[0x0c];
+ uint32_t clk_src_top10;
+ uint32_t clk_src_top11;
+ uint32_t clk_src_top12;
+ uint8_t res70[0x74];
+ uint32_t clk_src_mask_top0;
+ uint32_t clk_src_mask_top1;
+ uint32_t clk_src_mask_top2;
+ uint8_t res71[0x10];
+ uint32_t clk_src_mask_top7;
+ uint8_t res72[0xc];
+ uint32_t clk_src_mask_disp10; /* 0x1002032c */
+ uint8_t res73[0x4];
+ uint32_t clk_src_mask_mau;
+ uint8_t res74[0x8];
+ uint32_t clk_src_mask_fsys;
+ uint8_t res75[0xc];
+ uint32_t clk_src_mask_peric0;
+ uint32_t clk_src_mask_peric1;
+ uint8_t res76[0x18];
+ uint32_t clk_src_mask_isp;
+ uint8_t res77[0x8c];
+ uint32_t clk_mux_stat_top0; /* 0x10020400 */
+ uint32_t clk_mux_stat_top1;
+ uint32_t clk_mux_stat_top2;
+ uint32_t clk_mux_stat_top3;
+ uint32_t clk_mux_stat_top4;
+ uint32_t clk_mux_stat_top5;
+ uint32_t clk_mux_stat_top6;
+ uint32_t clk_mux_stat_top7;
+ uint8_t res78[0x60];
+ uint32_t clk_mux_stat_top10;
+ uint32_t clk_mux_stat_top11;
+ uint32_t clk_mux_stat_top12;
+ uint8_t res79[0x74];
+ uint32_t clk_div_top0; /* 0x10020500 */
+ uint32_t clk_div_top1;
+ uint32_t clk_div_top2;
+ uint8_t res80[0x20];
+ uint32_t clk_div_disp10;
+ uint8_t res81[0x14];
+ uint32_t clk_div_mau;
+ uint32_t clk_div_fsys0;
+ uint32_t clk_div_fsys1;
+ uint32_t clk_div_fsys2;
+ uint8_t res82[0x4];
+ uint32_t clk_div_peric0;
+ uint32_t clk_div_peric1;
+ uint32_t clk_div_peric2;
+ uint32_t clk_div_peric3;
+ uint32_t clk_div_peric4; /* 0x10020568 */
+ uint8_t res83[0x14];
+ uint32_t clk_div_isp0;
+ uint32_t clk_div_isp1;
+ uint8_t res84[0x8];
+ uint32_t clkdiv2_ratio;
+ uint8_t res850[0xc];
+ uint32_t clkdiv4_ratio;
+ uint8_t res85[0x5c];
+ uint32_t clk_div_stat_top0;
+ uint32_t clk_div_stat_top1;
+ uint32_t clk_div_stat_top2;
+ uint8_t res86[0x20];
+ uint32_t clk_div_stat_disp10;
+ uint8_t res87[0x14];
+ uint32_t clk_div_stat_mau; /* 0x10020644 */
+ uint32_t clk_div_stat_fsys0;
+ uint32_t clk_div_stat_fsys1;
+ uint32_t clk_div_stat_fsys2;
+ uint8_t res88[0x4];
+ uint32_t clk_div_stat_peric0;
+ uint32_t clk_div_stat_peric1;
+ uint32_t clk_div_stat_peric2;
+ uint32_t clk_div_stat_peric3;
+ uint32_t clk_div_stat_peric4;
+ uint8_t res89[0x14];
+ uint32_t clk_div_stat_isp0;
+ uint32_t clk_div_stat_isp1;
+ uint8_t res90[0x8];
+ uint32_t clkdiv2_stat0;
+ uint8_t res91[0xc];
+ uint32_t clkdiv4_stat;
+ uint8_t res92[0x5c];
+ uint32_t clk_gate_bus_top; /* 0x10020700 */
+ uint8_t res93[0xc];
+ uint32_t clk_gate_bus_gscl0;
+ uint8_t res94[0xc];
+ uint32_t clk_gate_bus_gscl1;
+ uint8_t res95[0x4];
+ uint32_t clk_gate_bus_disp1;
+ uint8_t res96[0x4];
+ uint32_t clk_gate_bus_wcore;
+ uint32_t clk_gate_bus_mfc;
+ uint32_t clk_gate_bus_g3d;
+ uint32_t clk_gate_bus_gen;
+ uint32_t clk_gate_bus_fsys0;
+ uint32_t clk_gate_bus_fsys1;
+ uint32_t clk_gate_bus_fsys2;
+ uint32_t clk_gate_bus_mscl;
+ uint32_t clk_gate_bus_peric;
+ uint32_t clk_gate_bus_peric1;
+ uint8_t res97[0x8];
+ uint32_t clk_gate_bus_peris0;
+ uint32_t clk_gate_bus_peris1; /* 0x10020764 */
+ uint8_t res98[0x8];
+ uint32_t clk_gate_bus_noc;
+ uint8_t res99[0xac];
+ uint32_t clk_gate_top_sclk_gscl;
+ uint8_t res1000[0x4];
+ uint32_t clk_gate_top_sclk_disp1;
+ uint8_t res100[0x10];
+ uint32_t clk_gate_top_sclk_mau;
+ uint32_t clk_gate_top_sclk_fsys;
+ uint8_t res101[0xc];
+ uint32_t clk_gate_top_sclk_peric;
+ uint8_t res102[0xc];
+ uint32_t clk_gate_top_sclk_cperi;
+ uint8_t res103[0xc];
+ uint32_t clk_gate_top_sclk_isp;
+ uint8_t res104[0x9c];
+ uint32_t clk_gate_ip_gscl0;
+ uint8_t res105[0xc];
+ uint32_t clk_gate_ip_gscl1;
+ uint8_t res106[0x4];
+ uint32_t clk_gate_ip_disp1;
+ uint32_t clk_gate_ip_mfc;
+ uint32_t clk_gate_ip_g3d;
+ uint32_t clk_gate_ip_gen; /* 0x10020934 */
+ uint8_t res107[0xc];
+ uint32_t clk_gate_ip_fsys;
+ uint8_t res108[0x8];
+ uint32_t clk_gate_ip_peric;
+ uint8_t res109[0xc];
+ uint32_t clk_gate_ip_peris;
+ uint8_t res110[0xc];
+ uint32_t clk_gate_ip_mscl;
+ uint8_t res111[0xc];
+ uint32_t clk_gate_ip_block;
+ uint8_t res112[0xc];
+ uint32_t bypass;
+ uint8_t res113[0x6c];
+ uint32_t clkout_cmu_top;
+ uint32_t clkout_cmu_top_div_stat;
+ uint8_t res114[0xf8];
+ uint32_t clkout_top_spare0;
+ uint32_t clkout_top_spare1;
+ uint32_t clkout_top_spare2;
+ uint32_t clkout_top_spare3;
+ uint8_t res115[0x34e0];
+ uint32_t clkout_top_version;
+ uint8_t res116[0xc01c];
+ uint32_t bpll_lock; /* 0x10030010 */
+ uint8_t res117[0xfc];
+ uint32_t bpll_con0;
+ uint32_t bpll_con1;
+ uint8_t res118[0xe8];
+ uint32_t clk_src_cdrex;
+ uint8_t res119[0x1fc];
+ uint32_t clk_mux_stat_cdrex;
+ uint8_t res120[0xfc];
+ uint32_t clk_div_cdrex0;
+ uint32_t clk_div_cdrex1;
+ uint8_t res121[0xf8];
+ uint32_t clk_div_stat_cdrex;
+ uint8_t res1211[0xfc];
+ uint32_t clk_gate_bus_cdrex;
+ uint32_t clk_gate_bus_cdrex1;
+ uint8_t res122[0x1f8];
+ uint32_t clk_gate_ip_cdrex;
+ uint8_t res123[0x10];
+ uint32_t dmc_freq_ctrl; /* 0x10030914 */
+ uint8_t res124[0x4];
+ uint32_t pause;
+ uint32_t ddrphy_lock_ctrl;
+ uint8_t res125[0xdc];
+ uint32_t clkout_cmu_cdrex;
+ uint32_t clkout_cmu_cdrex_div_stat;
+ uint8_t res126[0x8];
+ uint32_t lpddr3phy_ctrl;
+ uint32_t lpddr3phy_con0;
+ uint32_t lpddr3phy_con1;
+ uint32_t lpddr3phy_con2;
+ uint32_t lpddr3phy_con3;
+ uint32_t lpddr3phy_con4;
+ uint32_t lpddr3phy_con5; /* 0x10030a28 */
+ uint32_t pll_div2_sel;
+ uint8_t res127[0xd0];
+ uint32_t cmu_cdrex_spare0;
+ uint32_t cmu_cdrex_spare1;
+ uint32_t cmu_cdrex_spare2;
+ uint32_t cmu_cdrex_spare3;
+ uint32_t cmu_cdrex_spare4;
+ uint8_t res128[0x34dc];
+ uint32_t cmu_cdrex_version; /* 0x10033ff0 */
+ uint8_t res129[0x400c];
+ uint32_t kpll_lock;
+ uint8_t res130[0xfc];
+ uint32_t kpll_con0;
+ uint32_t kpll_con1;
+ uint8_t res131[0xf8];
+ uint32_t clk_src_kfc;
+ uint8_t res132[0x1fc];
+ uint32_t clk_mux_stat_kfc; /* 0x10038400 */
+ uint8_t res133[0xfc];
+ uint32_t clk_div_kfc0;
+ uint8_t res134[0xfc];
+ uint32_t clk_div_stat_kfc0;
+ uint8_t res135[0xfc];
+ uint32_t clk_gate_bus_cpu_kfc;
+ uint8_t res136[0xfc];
+ uint32_t clk_gate_sclk_cpu_kfc;
+ uint8_t res137[0x1fc];
+ uint32_t clkout_cmu_kfc;
+ uint32_t clkout_cmu_kfc_div_stat;/* 0x10038a04 */
+ uint8_t res138[0x5f8];
+ uint32_t armclk_stopctrl_kfc;
+ uint8_t res139[0x4];
+ uint32_t armclk_ema_ctrl_kfc;
+ uint32_t armclk_ema_status_kfc;
+ uint8_t res140[0x10];
+ uint32_t pwr_ctrl_kfc;
+ uint32_t pwr_ctrl2_kfc;
+ uint8_t res141[0xd8];
+ uint32_t kpll_con0_l8;
+ uint32_t kpll_con0_l7;
+ uint32_t kpll_con0_l6;
+ uint32_t kpll_con0_l5;
+ uint32_t kpll_con0_l4;
+ uint32_t kpll_con0_l3;
+ uint32_t kpll_con0_l2;
+ uint32_t kpll_con0_l1;
+ uint32_t iem_control_kfc; /* 0x10039120 */
+ uint8_t res142[0xdc];
+ uint32_t kpll_con1_l8;
+ uint32_t kpll_con1_l7;
+ uint32_t kpll_con1_l6;
+ uint32_t kpll_con1_l5;
+ uint32_t kpll_con1_l4;
+ uint32_t kpll_con1_l3;
+ uint32_t kpll_con1_l2;
+ uint32_t kpll_con1_l1;
+ uint8_t res143[0xe0];
+ uint32_t clkdiv_iem_l8_kfc; /* 0x10039300 */
+ uint32_t clkdiv_iem_l7_kfc;
+ uint32_t clkdiv_iem_l6_kfc;
+ uint32_t clkdiv_iem_l5_kfc;
+ uint32_t clkdiv_iem_l4_kfc;
+ uint32_t clkdiv_iem_l3_kfc;
+ uint32_t clkdiv_iem_l2_kfc;
+ uint32_t clkdiv_iem_l1_kfc;
+ uint8_t res144[0xe0];
+ uint32_t l2_status_kfc;
+ uint8_t res145[0xc];
+ uint32_t cpu_status_kfc; /* 0x10039410 */
+ uint8_t res146[0xc];
+ uint32_t ptm_status_kfc;
+ uint8_t res147[0xbdc];
+ uint32_t cmu_kfc_spare0;
+ uint32_t cmu_kfc_spare1;
+ uint32_t cmu_kfc_spare2;
+ uint32_t cmu_kfc_spare3;
+ uint32_t cmu_kfc_spare4;
+ uint8_t res148[0x1fdc];
+ uint32_t cmu_kfc_version; /* 0x1003bff0 */
};
struct exynos5_mct_regs {
@@ -618,7 +1114,6 @@ struct arm_clk_ratios *get_arm_clk_ratios(void);
* Initialize clock for the device
*/
struct mem_timings;
-void system_clock_init(struct mem_timings *mem,
- struct arm_clk_ratios *arm_clk_ratio);
+void system_clock_init(void);
#endif
diff --git a/src/cpu/samsung/exynos5420/clock.c b/src/cpu/samsung/exynos5420/clock.c
index e199e6bc37..fd15486090 100644
--- a/src/cpu/samsung/exynos5420/clock.c
+++ b/src/cpu/samsung/exynos5420/clock.c
@@ -28,100 +28,6 @@
/* input clock of PLL: SMDK5420 has 24MHz input clock */
#define CONFIG_SYS_CLK_FREQ 24000000
-static struct arm_clk_ratios arm_clk_ratios[] = {
- {
- .arm_freq_mhz = 600,
-
- .apll_mdiv = 0xc8,
- .apll_pdiv = 0x4,
- .apll_sdiv = 0x1,
-
- .arm2_ratio = 0x0,
- .apll_ratio = 0x1,
- .pclk_dbg_ratio = 0x1,
- .atb_ratio = 0x2,
- .periph_ratio = 0x7,
- .acp_ratio = 0x7,
- .cpud_ratio = 0x1,
- .arm_ratio = 0x0,
- }, {
- .arm_freq_mhz = 800,
-
- .apll_mdiv = 0x64,
- .apll_pdiv = 0x3,
- .apll_sdiv = 0x0,
-
- .arm2_ratio = 0x0,
- .apll_ratio = 0x1,
- .pclk_dbg_ratio = 0x1,
- .atb_ratio = 0x3,
- .periph_ratio = 0x7,
- .acp_ratio = 0x7,
- .cpud_ratio = 0x2,
- .arm_ratio = 0x0,
- }, {
- .arm_freq_mhz = 1000,
-
- .apll_mdiv = 0x7d,
- .apll_pdiv = 0x3,
- .apll_sdiv = 0x0,
-
- .arm2_ratio = 0x0,
- .apll_ratio = 0x1,
- .pclk_dbg_ratio = 0x1,
- .atb_ratio = 0x4,
- .periph_ratio = 0x7,
- .acp_ratio = 0x7,
- .cpud_ratio = 0x2,
- .arm_ratio = 0x0,
- }, {
- .arm_freq_mhz = 1200,
-
- .apll_mdiv = 0x96,
- .apll_pdiv = 0x3,
- .apll_sdiv = 0x0,
-
- .arm2_ratio = 0x0,
- .apll_ratio = 0x3,
- .pclk_dbg_ratio = 0x1,
- .atb_ratio = 0x5,
- .periph_ratio = 0x7,
- .acp_ratio = 0x7,
- .cpud_ratio = 0x3,
- .arm_ratio = 0x0,
- }, {
- .arm_freq_mhz = 1400,
-
- .apll_mdiv = 0xaf,
- .apll_pdiv = 0x3,
- .apll_sdiv = 0x0,
-
- .arm2_ratio = 0x0,
- .apll_ratio = 0x3,
- .pclk_dbg_ratio = 0x1,
- .atb_ratio = 0x6,
- .periph_ratio = 0x7,
- .acp_ratio = 0x7,
- .cpud_ratio = 0x3,
- .arm_ratio = 0x0,
- }, {
- .arm_freq_mhz = 1700,
-
- .apll_mdiv = 0x1a9,
- .apll_pdiv = 0x6,
- .apll_sdiv = 0x0,
-
- .arm2_ratio = 0x0,
- .apll_ratio = 0x3,
- .pclk_dbg_ratio = 0x1,
- .atb_ratio = 0x6,
- .periph_ratio = 0x7,
- .acp_ratio = 0x7,
- .cpud_ratio = 0x3,
- .arm_ratio = 0x0,
- }
-};
-
/* src_bit div_bit prediv_bit */
static struct clk_bit_info clk_bit_info[PERIPH_ID_COUNT] = {
{0, 4, 0, -1},
@@ -173,8 +79,8 @@ static struct st_epll_con_val epll_div[] = {
/* exynos5: return pll clock frequency */
unsigned long get_pll_clk(int pllreg)
{
- struct exynos5_clock *clk =
- samsung_get_base_clock();
+ struct exynos5420_clock *clk =
+ (struct exynos5420_clock *)samsung_get_base_clock();
unsigned long r, m, p, s, k = 0, mask, fout;
unsigned int freq;
@@ -182,9 +88,6 @@ unsigned long get_pll_clk(int pllreg)
case APLL:
r = readl(&clk->apll_con0);
break;
- case BPLL:
- r = readl(&clk->bpll_con0);
- break;
case MPLL:
r = readl(&clk->mpll_con0);
break;
@@ -196,6 +99,16 @@ unsigned long get_pll_clk(int pllreg)
r = readl(&clk->vpll_con0);
k = readl(&clk->vpll_con1);
break;
+ case BPLL:
+ r = readl(&clk->bpll_con0);
+ break;
+ case RPLL:
+ r = readl(&clk->rpll_con0);
+ k = readl(&clk->rpll_con1);
+ break;
+ case SPLL:
+ r = readl(&clk->spll_con0);
+ break;
default:
printk(BIOS_DEBUG, "Unsupported PLL (%d)\n", pllreg);
return 0;
@@ -207,7 +120,8 @@ unsigned long get_pll_clk(int pllreg)
* EPLL_CON: MIDV [24:16]
* VPLL_CON: MIDV [24:16]
*/
- if (pllreg == APLL || pllreg == BPLL || pllreg == MPLL)
+ if (pllreg == APLL || pllreg == BPLL || pllreg == MPLL ||
+ pllreg == SPLL)
mask = 0x3ff;
else
mask = 0x1ff;
@@ -221,7 +135,7 @@ unsigned long get_pll_clk(int pllreg)
freq = CONFIG_SYS_CLK_FREQ;
- if (pllreg == EPLL) {
+ if (pllreg == EPLL || pllreg == RPLL) {
k = k & 0xffff;
/* FOUT = (MDIV + K / 65536) * FIN / (PDIV * 2^SDIV) */
fout = (m + k / 65536) * (freq / (p * (1 << s)));
@@ -239,11 +153,10 @@ unsigned long get_pll_clk(int pllreg)
unsigned long clock_get_periph_rate(enum periph_id peripheral)
{
- struct exynos5_clock *clk =
- samsung_get_base_clock();
struct clk_bit_info *bit_info = &clk_bit_info[peripheral];
unsigned long sclk, sub_clk;
unsigned int src, div, sub_div;
+ struct exynos5_clock *clk = samsung_get_base_clock();
switch (peripheral) {
case PERIPH_ID_UART0:
@@ -275,10 +188,6 @@ unsigned long clock_get_periph_rate(enum periph_id peripheral)
src = readl(&clk->sclk_src_isp);
div = readl(&clk->sclk_div_isp);
break;
- case PERIPH_ID_SATA:
- src = readl(&clk->src_fsys);
- div = readl(&clk->div_fsys0);
- break;
case PERIPH_ID_SDMMC0:
case PERIPH_ID_SDMMC1:
case PERIPH_ID_SDMMC2:
@@ -303,26 +212,27 @@ unsigned long clock_get_periph_rate(enum periph_id peripheral)
return -1;
};
- src = (src >> bit_info->src_bit) & ((1 << bit_info->n_src_bits) - 1);
- if (peripheral == PERIPH_ID_SATA) {
- if (src)
- sclk = get_pll_clk(BPLL);
- else
- sclk = get_pll_clk(MPLL);
- } else {
- if (src == SRC_MPLL)
- sclk = get_pll_clk(MPLL);
- else if (src == SRC_EPLL)
- sclk = get_pll_clk(EPLL);
- else if (src == SRC_VPLL)
- sclk = get_pll_clk(VPLL);
- else
- return 0;
+ src = (src >> bit_info->src_bit) & 0xf;
+
+ switch (src) {
+ case EXYNOS_SRC_MPLL:
+ sclk = get_pll_clk(MPLL);
+ break;
+ case EXYNOS_SRC_EPLL:
+ sclk = get_pll_clk(EPLL);
+ break;
+ case EXYNOS_SRC_VPLL:
+ sclk = get_pll_clk(VPLL);
+ break;
+ default:
+ return 0;
}
+ /* Ratio clock division for this peripheral */
sub_div = (div >> bit_info->div_bit) & 0xf;
sub_clk = sclk / (sub_div + 1);
+ /* Pre-ratio clock division for SDMMC0 and 2 */
if (peripheral == PERIPH_ID_SDMMC0 || peripheral == PERIPH_ID_SDMMC2) {
div = (div >> bit_info->prediv_bit) & 0xff;
return sub_clk / (div + 1);
@@ -334,8 +244,7 @@ unsigned long clock_get_periph_rate(enum periph_id peripheral)
/* exynos5: return ARM clock frequency */
unsigned long get_arm_clk(void)
{
- struct exynos5_clock *clk =
- samsung_get_base_clock();
+ struct exynos5_clock *clk = samsung_get_base_clock();
unsigned long div;
unsigned long armclk;
unsigned int arm_ratio;
@@ -353,45 +262,20 @@ unsigned long get_arm_clk(void)
return armclk;
}
-struct arm_clk_ratios *get_arm_clk_ratios(void)
-{
- struct arm_clk_ratios *arm_ratio;
- unsigned long arm_freq = 1700; /* FIXME: use get_arm_clk() */
- int i;
-
- for (i = 0, arm_ratio = arm_clk_ratios; i < ARRAY_SIZE(arm_clk_ratios);
- i++, arm_ratio++) {
- if (arm_ratio->arm_freq_mhz == arm_freq)
- return arm_ratio;
- }
-
- return NULL;
-}
-
/* exynos5: set the mmc clock */
void set_mmc_clk(int dev_index, unsigned int div)
{
- struct exynos5_clock *clk =
- samsung_get_base_clock();
- unsigned int *addr;
- unsigned int val;
+ struct exynos5420_clock *clk =
+ (struct exynos5420_clock *)samsung_get_base_clock();
+ void *addr;
+ unsigned int val, shift;
- /*
- * CLK_DIV_FSYS1
- * MMC0_PRE_RATIO [15:8], MMC1_PRE_RATIO [31:24]
- * CLK_DIV_FSYS2
- * MMC2_PRE_RATIO [15:8], MMC3_PRE_RATIO [31:24]
- */
- if (dev_index < 2) {
- addr = &clk->div_fsys1;
- } else {
- addr = &clk->div_fsys2;
- dev_index -= 2;
- }
+ addr = &clk->clk_div_fsys1;
+ shift = dev_index * 10;
val = readl(addr);
- val &= ~(0xff << ((dev_index << 4) + 8));
- val |= (div & 0xff) << ((dev_index << 4) + 8);
+ val &= ~(0x3ff << shift);
+ val |= (div & 0x3ff) << shift;
writel(val, addr);
}
diff --git a/src/cpu/samsung/exynos5420/clock_init.c b/src/cpu/samsung/exynos5420/clock_init.c
index 2986cabc24..0a13c9ec64 100644
--- a/src/cpu/samsung/exynos5420/clock_init.c
+++ b/src/cpu/samsung/exynos5420/clock_init.c
@@ -26,420 +26,175 @@
#include "dp.h"
#include "setup.h"
-void system_clock_init(struct mem_timings *mem,
- struct arm_clk_ratios *arm_clk_ratio)
+void system_clock_init(void)
{
- struct exynos5_clock *clk = (struct exynos5_clock *)EXYNOS5_CLOCK_BASE;
+ struct exynos5420_clock *clk =
+ (struct exynos5420_clock *)EXYNOS5_CLOCK_BASE;
struct exynos5_mct_regs *mct_regs =
(struct exynos5_mct_regs *)EXYNOS5_MULTI_CORE_TIMER_BASE;
- u32 val, tmp;
+ u32 val;
/* Turn on the MCT as early as possible. */
mct_regs->g_tcon |= (1 << 8);
- clrbits_le32(&clk->src_cpu, MUX_APLL_SEL_MASK);
- do {
- val = readl(&clk->mux_stat_cpu);
- } while ((val | MUX_APLL_SEL_MASK) != val);
-
- clrbits_le32(&clk->src_core1, MUX_MPLL_SEL_MASK);
- do {
- val = readl(&clk->mux_stat_core1);
- } while ((val | MUX_MPLL_SEL_MASK) != val);
-
- clrbits_le32(&clk->src_top2, MUX_CPLL_SEL_MASK);
- clrbits_le32(&clk->src_top2, MUX_EPLL_SEL_MASK);
- clrbits_le32(&clk->src_top2, MUX_VPLL_SEL_MASK);
- clrbits_le32(&clk->src_top2, MUX_GPLL_SEL_MASK);
- tmp = MUX_CPLL_SEL_MASK | MUX_EPLL_SEL_MASK | MUX_VPLL_SEL_MASK
- | MUX_GPLL_SEL_MASK;
- do {
- val = readl(&clk->mux_stat_top2);
- } while ((val | tmp) != val);
-
- clrbits_le32(&clk->src_cdrex, MUX_BPLL_SEL_MASK);
- do {
- val = readl(&clk->mux_stat_cdrex);
- } while ((val | MUX_BPLL_SEL_MASK) != val);
-
/* PLL locktime */
writel(APLL_LOCK_VAL, &clk->apll_lock);
-
writel(MPLL_LOCK_VAL, &clk->mpll_lock);
-
writel(BPLL_LOCK_VAL, &clk->bpll_lock);
-
writel(CPLL_LOCK_VAL, &clk->cpll_lock);
-
- writel(GPLL_LOCK_VAL, &clk->gpll_lock);
-
+ writel(DPLL_LOCK_VAL, &clk->dpll_lock);
writel(EPLL_LOCK_VAL, &clk->epll_lock);
-
writel(VPLL_LOCK_VAL, &clk->vpll_lock);
+ writel(IPLL_LOCK_VAL, &clk->ipll_lock);
+ writel(SPLL_LOCK_VAL, &clk->spll_lock);
+ writel(KPLL_LOCK_VAL, &clk->kpll_lock);
+
+ setbits_le32(&clk->clk_src_cpu, MUX_HPM_SEL_MASK);
- writel(CLK_REG_DISABLE, &clk->pll_div2_sel);
-
- writel(MUX_HPM_SEL_MASK, &clk->src_cpu);
- do {
- val = readl(&clk->mux_stat_cpu);
- } while ((val | HPM_SEL_SCLK_MPLL) != val);
-
- val = arm_clk_ratio->arm2_ratio << 28
- | arm_clk_ratio->apll_ratio << 24
- | arm_clk_ratio->pclk_dbg_ratio << 20
- | arm_clk_ratio->atb_ratio << 16
- | arm_clk_ratio->periph_ratio << 12
- | arm_clk_ratio->acp_ratio << 8
- | arm_clk_ratio->cpud_ratio << 4
- | arm_clk_ratio->arm_ratio;
- writel(val, &clk->div_cpu0);
- do {
- val = readl(&clk->div_stat_cpu0);
- } while (0 != val);
-
- writel(CLK_DIV_CPU1_VAL, &clk->div_cpu1);
- do {
- val = readl(&clk->div_stat_cpu1);
- } while (0 != val);
+ writel(0, &clk->clk_src_top6);
+
+ writel(0, &clk->clk_src_cdrex);
+ writel(SRC_KFC_HPM_SEL, &clk->clk_src_kfc);
+ writel(HPM_RATIO, &clk->clk_div_cpu1);
+ writel(CLK_DIV_CPU0_VAL, &clk->clk_div_cpu0);
/* Set APLL */
writel(APLL_CON1_VAL, &clk->apll_con1);
- val = set_pll(arm_clk_ratio->apll_mdiv, arm_clk_ratio->apll_pdiv,
- arm_clk_ratio->apll_sdiv);
+ val = set_pll(0xc8, 0x3, 0x1);
writel(val, &clk->apll_con0);
- while ((readl(&clk->apll_con0) & APLL_CON0_LOCKED) == 0)
+ while ((readl(&clk->apll_con0) & PLL_LOCKED) == 0)
+ ;
+
+ writel(SRC_KFC_HPM_SEL, &clk->clk_src_kfc);
+ writel(CLK_DIV_KFC_VAL, &clk->clk_div_kfc0);
+
+ /* Set KPLL*/
+ writel(KPLL_CON1_VAL, &clk->kpll_con1);
+ val = set_pll(0xc8, 0x2, 0x2);
+ writel(val, &clk->kpll_con0);
+ while ((readl(&clk->kpll_con0) & PLL_LOCKED) == 0)
;
/* Set MPLL */
writel(MPLL_CON1_VAL, &clk->mpll_con1);
- val = set_pll(mem->mpll_mdiv, mem->mpll_pdiv, mem->mpll_sdiv);
+ val = set_pll(0xc8, 0x3, 0x1);
writel(val, &clk->mpll_con0);
- while ((readl(&clk->mpll_con0) & MPLL_CON0_LOCKED) == 0)
- ;
-
- /*
- * Configure MUX_MPLL_FOUT to choose the direct clock source
- * path and avoid the fixed DIV/2 block to save power
- */
- setbits_le32(&clk->pll_div2_sel, MUX_MPLL_FOUT_SEL);
-
- /* Set BPLL */
- if (mem->use_bpll) {
- writel(BPLL_CON1_VAL, &clk->bpll_con1);
- val = set_pll(mem->bpll_mdiv, mem->bpll_pdiv, mem->bpll_sdiv);
- writel(val, &clk->bpll_con0);
- while ((readl(&clk->bpll_con0) & BPLL_CON0_LOCKED) == 0)
- ;
-
- setbits_le32(&clk->pll_div2_sel, MUX_BPLL_FOUT_SEL);
- }
-
- /* Set CPLL */
- writel(CPLL_CON1_VAL, &clk->cpll_con1);
- val = set_pll(mem->cpll_mdiv, mem->cpll_pdiv, mem->cpll_sdiv);
- writel(val, &clk->cpll_con0);
- while ((readl(&clk->cpll_con0) & CPLL_CON0_LOCKED) == 0)
+ while ((readl(&clk->mpll_con0) & PLL_LOCKED) == 0)
;
- /* Set GPLL */
- writel(GPLL_CON1_VAL, &clk->gpll_con1);
- val = set_pll(mem->gpll_mdiv, mem->gpll_pdiv, mem->gpll_sdiv);
- writel(val, &clk->gpll_con0);
- while ((readl(&clk->gpll_con0) & GPLL_CON0_LOCKED) == 0)
+ /* Set DPLL */
+ writel(DPLL_CON1_VAL, &clk->dpll_con1);
+ val = set_pll(0xc8, 0x2, 0x2);
+ writel(val, &clk->dpll_con0);
+ while ((readl(&clk->dpll_con0) & PLL_LOCKED) == 0)
;
/* Set EPLL */
writel(EPLL_CON2_VAL, &clk->epll_con2);
writel(EPLL_CON1_VAL, &clk->epll_con1);
- val = set_pll(mem->epll_mdiv, mem->epll_pdiv, mem->epll_sdiv);
+ val = set_pll(0x64, 0x2, 0x1);
writel(val, &clk->epll_con0);
- while ((readl(&clk->epll_con0) & EPLL_CON0_LOCKED) == 0)
- ;
-
- /* Set VPLL */
- writel(VPLL_CON2_VAL, &clk->vpll_con2);
- writel(VPLL_CON1_VAL, &clk->vpll_con1);
- val = set_pll(mem->vpll_mdiv, mem->vpll_pdiv, mem->vpll_sdiv);
- writel(val, &clk->vpll_con0);
- while ((readl(&clk->vpll_con0) & VPLL_CON0_LOCKED) == 0)
- ;
-
- writel(CLK_SRC_CORE0_VAL, &clk->src_core0);
- writel(CLK_DIV_CORE0_VAL, &clk->div_core0);
- while (readl(&clk->div_stat_core0) != 0)
- ;
-
- writel(CLK_DIV_CORE1_VAL, &clk->div_core1);
- while (readl(&clk->div_stat_core1) != 0)
- ;
-
- writel(CLK_DIV_SYSRGT_VAL, &clk->div_sysrgt);
- while (readl(&clk->div_stat_sysrgt) != 0)
+ while ((readl(&clk->epll_con0) & PLL_LOCKED) == 0)
;
- writel(CLK_DIV_ACP_VAL, &clk->div_acp);
- while (readl(&clk->div_stat_acp) != 0)
- ;
-
- writel(CLK_DIV_SYSLFT_VAL, &clk->div_syslft);
- while (readl(&clk->div_stat_syslft) != 0)
- ;
-
- writel(CLK_SRC_TOP0_VAL, &clk->src_top0);
- writel(CLK_SRC_TOP1_VAL, &clk->src_top1);
- writel(TOP2_VAL, &clk->src_top2);
- writel(CLK_SRC_TOP3_VAL, &clk->src_top3);
-
- writel(CLK_DIV_TOP0_VAL, &clk->div_top0);
- while (readl(&clk->div_stat_top0))
- ;
-
- writel(CLK_DIV_TOP1_VAL, &clk->div_top1);
- while (readl(&clk->div_stat_top1))
- ;
-
- writel(CLK_SRC_LEX_VAL, &clk->src_lex);
- while (1) {
- val = readl(&clk->mux_stat_lex);
- if (val == (val | 1))
- break;
- }
-
- writel(CLK_DIV_LEX_VAL, &clk->div_lex);
- while (readl(&clk->div_stat_lex))
- ;
-
- writel(CLK_DIV_R0X_VAL, &clk->div_r0x);
- while (readl(&clk->div_stat_r0x))
- ;
-
- writel(CLK_DIV_R0X_VAL, &clk->div_r0x);
- while (readl(&clk->div_stat_r0x))
- ;
-
- writel(CLK_DIV_R1X_VAL, &clk->div_r1x);
- while (readl(&clk->div_stat_r1x))
+ /* Set CPLL */
+ writel(CPLL_CON1_VAL, &clk->cpll_con1);
+ val = set_pll(0x6f, 0x2, 0x1);
+ writel(val, &clk->cpll_con0);
+ while ((readl(&clk->cpll_con0) & PLL_LOCKED) == 0)
;
- if (mem->use_bpll) {
- writel(MUX_BPLL_SEL_MASK | MUX_MCLK_CDREX_SEL |
- MUX_MCLK_DPHY_SEL, &clk->src_cdrex);
- } else {
- writel(CLK_REG_DISABLE, &clk->src_cdrex);
- }
-
- writel(CLK_DIV_CDREX_VAL, &clk->div_cdrex);
- while (readl(&clk->div_stat_cdrex))
+ /* Set IPLL */
+ writel(IPLL_CON1_VAL, &clk->ipll_con1);
+ val = set_pll(0xB9, 0x3, 0x2);
+ writel(val, &clk->ipll_con0);
+ while ((readl(&clk->ipll_con0) & PLL_LOCKED) == 0)
;
- val = readl(&clk->src_cpu);
- val |= CLK_SRC_CPU_VAL;
- writel(val, &clk->src_cpu);
-
- val = readl(&clk->src_top2);
- val |= CLK_SRC_TOP2_VAL;
- writel(val, &clk->src_top2);
-
- val = readl(&clk->src_core1);
- val |= CLK_SRC_CORE1_VAL;
- writel(val, &clk->src_core1);
-
- writel(CLK_SRC_FSYS0_VAL, &clk->src_fsys);
- writel(CLK_DIV_FSYS0_VAL, &clk->div_fsys0);
- while (readl(&clk->div_stat_fsys0))
+ /* Set VPLL */
+ writel(VPLL_CON1_VAL, &clk->vpll_con1);
+ val = set_pll(0xd7, 0x3, 0x2);
+ writel(val, &clk->vpll_con0);
+ while ((readl(&clk->vpll_con0) & PLL_LOCKED) == 0)
;
- writel(CLK_REG_DISABLE, &clk->clkout_cmu_cpu);
- writel(CLK_REG_DISABLE, &clk->clkout_cmu_core);
- writel(CLK_REG_DISABLE, &clk->clkout_cmu_acp);
- writel(CLK_REG_DISABLE, &clk->clkout_cmu_top);
- writel(CLK_REG_DISABLE, &clk->clkout_cmu_lex);
- writel(CLK_REG_DISABLE, &clk->clkout_cmu_r0x);
- writel(CLK_REG_DISABLE, &clk->clkout_cmu_r1x);
- writel(CLK_REG_DISABLE, &clk->clkout_cmu_cdrex);
-
- writel(CLK_SRC_PERIC0_VAL, &clk->src_peric0);
- writel(CLK_DIV_PERIC0_VAL, &clk->div_peric0);
-
- writel(CLK_SRC_PERIC1_VAL, &clk->src_peric1);
- writel(CLK_DIV_PERIC1_VAL, &clk->div_peric1);
- writel(CLK_DIV_PERIC2_VAL, &clk->div_peric2);
- writel(SCLK_SRC_ISP_VAL, &clk->sclk_src_isp);
- writel(SCLK_DIV_ISP_VAL, &clk->sclk_div_isp);
- writel(CLK_DIV_ISP0_VAL, &clk->div_isp0);
- writel(CLK_DIV_ISP1_VAL, &clk->div_isp1);
- writel(CLK_DIV_ISP2_VAL, &clk->div_isp2);
-
- /* FIMD1 SRC CLK SELECTION */
- writel(CLK_SRC_DISP1_0_VAL, &clk->src_disp1_0);
-
- val = MMC2_PRE_RATIO_VAL << MMC2_PRE_RATIO_OFFSET
- | MMC2_RATIO_VAL << MMC2_RATIO_OFFSET
- | MMC3_PRE_RATIO_VAL << MMC3_PRE_RATIO_OFFSET
- | MMC3_RATIO_VAL << MMC3_RATIO_OFFSET;
- writel(val, &clk->div_fsys2);
+ /* Set BPLL */
+ writel(BPLL_CON1_VAL, &clk->bpll_con1);
+ val = set_pll(0xc8, 0x3, 0x1);
+ writel(val, &clk->bpll_con0);
+ while ((readl(&clk->bpll_con0) & PLL_LOCKED) == 0)
+ ;
+
+ /* Set SPLL */
+ writel(SPLL_CON1_VAL, &clk->spll_con1);
+ val = set_pll(0xc8, 0x2, 0x3);
+ writel(val, &clk->spll_con0);
+ while ((readl(&clk->spll_con0) & PLL_LOCKED) == 0)
+ ;
+
+ writel(CLK_DIV_CDREX0_VAL, &clk->clk_div_cdrex0);
+ writel(CLK_DIV_CDREX1_VAL, &clk->clk_div_cdrex1);
+
+ writel(CLK_SRC_TOP0_VAL, &clk->clk_src_top0);
+ writel(CLK_SRC_TOP1_VAL, &clk->clk_src_top1);
+ writel(CLK_SRC_TOP2_VAL, &clk->clk_src_top2);
+ writel(CLK_SRC_TOP7_VAL, &clk->clk_src_top7);
+
+ writel(CLK_DIV_TOP0_VAL, &clk->clk_div_top0);
+ writel(CLK_DIV_TOP1_VAL, &clk->clk_div_top1);
+ writel(CLK_DIV_TOP2_VAL, &clk->clk_div_top2);
+
+ writel(0, &clk->clk_src_top10);
+ writel(0, &clk->clk_src_top11);
+ writel(0, &clk->clk_src_top12);
+
+ writel(CLK_SRC_TOP3_VAL, &clk->clk_src_top3);
+ writel(CLK_SRC_TOP4_VAL, &clk->clk_src_top4);
+ writel(CLK_SRC_TOP5_VAL, &clk->clk_src_top5);
+
+ /* DISP1 BLK CLK SELECTION */
+ writel(CLK_SRC_DISP1_0_VAL, &clk->clk_src_disp10);
+ writel(CLK_DIV_DISP1_0_VAL, &clk->clk_div_disp10);
+
+ /* AUDIO BLK */
+ writel(AUDIO0_SEL_EPLL, &clk->clk_src_mau);
+ writel(DIV_MAU_VAL, &clk->clk_div_mau);
+
+ /* FSYS */
+ writel(CLK_SRC_FSYS0_VAL, &clk->clk_src_fsys);
+ writel(CLK_DIV_FSYS0_VAL, &clk->clk_div_fsys0);
+ writel(CLK_DIV_FSYS1_VAL, &clk->clk_div_fsys1);
+ writel(CLK_DIV_FSYS2_VAL, &clk->clk_div_fsys2);
+
+ writel(CLK_SRC_ISP_VAL, &clk->clk_src_isp);
+ writel(CLK_DIV_ISP0_VAL, &clk->clk_div_isp0);
+ writel(CLK_DIV_ISP1_VAL, &clk->clk_div_isp1);
+
+ writel(CLK_SRC_PERIC0_VAL, &clk->clk_src_peric0);
+ writel(CLK_SRC_PERIC1_VAL, &clk->clk_src_peric1);
+
+ writel(CLK_DIV_PERIC0_VAL, &clk->clk_div_peric0);
+ writel(CLK_DIV_PERIC1_VAL, &clk->clk_div_peric1);
+ writel(CLK_DIV_PERIC2_VAL, &clk->clk_div_peric2);
+ writel(CLK_DIV_PERIC3_VAL, &clk->clk_div_peric3);
+ writel(CLK_DIV_PERIC4_VAL, &clk->clk_div_peric4);
+
+ writel(CLK_DIV2_RATIO, &clk->clkdiv2_ratio);
+ writel(CLK_DIV4_RATIO, &clk->clkdiv4_ratio);
+ writel(CLK_DIV_G2D, &clk->clk_div_g2d);
+
+ writel(CLK_SRC_CPU_VAL, &clk->clk_src_cpu);
+ writel(CLK_SRC_TOP3_VAL, &clk->clk_src_top6);
+ writel(CLK_SRC_CDREX_VAL, &clk->clk_src_cdrex);
+ writel(CLK_SRC_KFC_VAL, &clk->clk_src_kfc);
}
void clock_gate(void)
{
- struct exynos5_clock *clk = (struct exynos5_clock *)EXYNOS5_CLOCK_BASE;
-
- /* CLK_GATE_IP_SYSRGT */
- clrbits_le32(&clk->gate_ip_sysrgt, CLK_C2C_MASK);
-
- /* CLK_GATE_IP_ACP */
- clrbits_le32(&clk->gate_ip_acp, CLK_SMMUG2D_MASK |
- CLK_SMMUSSS_MASK |
- CLK_SMMUMDMA_MASK |
- CLK_ID_REMAPPER_MASK |
- CLK_G2D_MASK |
- CLK_SSS_MASK |
- CLK_MDMA_MASK |
- CLK_SECJTAG_MASK);
-
- /* CLK_GATE_BUS_SYSLFT */
- clrbits_le32(&clk->gate_bus_syslft, CLK_EFCLK_MASK);
-
- /* CLK_GATE_IP_ISP0 */
- clrbits_le32(&clk->gate_ip_isp0, CLK_UART_ISP_MASK |
- CLK_WDT_ISP_MASK |
- CLK_PWM_ISP_MASK |
- CLK_MTCADC_ISP_MASK |
- CLK_I2C1_ISP_MASK |
- CLK_I2C0_ISP_MASK |
- CLK_MPWM_ISP_MASK |
- CLK_MCUCTL_ISP_MASK |
- CLK_INT_COMB_ISP_MASK |
- CLK_SMMU_MCUISP_MASK |
- CLK_SMMU_SCALERP_MASK |
- CLK_SMMU_SCALERC_MASK |
- CLK_SMMU_FD_MASK |
- CLK_SMMU_DRC_MASK |
- CLK_SMMU_ISP_MASK |
- CLK_GICISP_MASK |
- CLK_ARM9S_MASK |
- CLK_MCUISP_MASK |
- CLK_SCALERP_MASK |
- CLK_SCALERC_MASK |
- CLK_FD_MASK |
- CLK_DRC_MASK |
- CLK_ISP_MASK);
-
- /* CLK_GATE_IP_ISP1 */
- clrbits_le32(&clk->gate_ip_isp1, CLK_SPI1_ISP_MASK |
- CLK_SPI0_ISP_MASK |
- CLK_SMMU3DNR_MASK |
- CLK_SMMUDIS1_MASK |
- CLK_SMMUDIS0_MASK |
- CLK_SMMUODC_MASK |
- CLK_3DNR_MASK |
- CLK_DIS_MASK |
- CLK_ODC_MASK);
-
- /* CLK_GATE_SCLK_ISP */
- clrbits_le32(&clk->gate_sclk_isp, SCLK_MPWM_ISP_MASK);
-
- /* CLK_GATE_IP_GSCL */
- clrbits_le32(&clk->gate_ip_gscl, CLK_SMMUFIMC_LITE2_MASK |
- CLK_SMMUFIMC_LITE1_MASK |
- CLK_SMMUFIMC_LITE0_MASK |
- CLK_SMMUGSCL3_MASK |
- CLK_SMMUGSCL2_MASK |
- CLK_SMMUGSCL1_MASK |
- CLK_SMMUGSCL0_MASK |
- CLK_GSCL_WRAP_B_MASK |
- CLK_GSCL_WRAP_A_MASK |
- CLK_CAMIF_TOP_MASK |
- CLK_GSCL3_MASK |
- CLK_GSCL2_MASK |
- CLK_GSCL1_MASK |
- CLK_GSCL0_MASK);
-
- /* CLK_GATE_IP_DISP1 */
- clrbits_le32(&clk->gate_ip_disp1, CLK_SMMUTVX_MASK |
- CLK_ASYNCTVX_MASK |
- CLK_HDMI_MASK |
- CLK_MIXER_MASK |
- CLK_DSIM1_MASK);
-
- /* CLK_GATE_IP_MFC */
- clrbits_le32(&clk->gate_ip_mfc, CLK_SMMUMFCR_MASK |
- CLK_SMMUMFCL_MASK |
- CLK_MFC_MASK);
-
- /* CLK_GATE_IP_GEN */
- clrbits_le32(&clk->gate_ip_gen, CLK_SMMUMDMA1_MASK |
- CLK_SMMUJPEG_MASK |
- CLK_SMMUROTATOR_MASK |
- CLK_MDMA1_MASK |
- CLK_JPEG_MASK |
- CLK_ROTATOR_MASK);
-
- /* CLK_GATE_IP_FSYS */
- clrbits_le32(&clk->gate_ip_fsys, CLK_WDT_IOP_MASK |
- CLK_SMMUMCU_IOP_MASK |
- CLK_SATA_PHY_I2C_MASK |
- CLK_SATA_PHY_CTRL_MASK |
- CLK_MCUCTL_MASK |
- CLK_NFCON_MASK |
- CLK_SMMURTIC_MASK |
- CLK_RTIC_MASK |
- CLK_MIPI_HSI_MASK |
- CLK_USBOTG_MASK |
- CLK_SATA_MASK |
- CLK_PDMA1_MASK |
- CLK_PDMA0_MASK |
- CLK_MCU_IOP_MASK);
-
- /* CLK_GATE_IP_PERIC */
- clrbits_le32(&clk->gate_ip_peric, CLK_HS_I2C3_MASK |
- CLK_HS_I2C2_MASK |
- CLK_HS_I2C1_MASK |
- CLK_HS_I2C0_MASK |
- CLK_AC97_MASK |
- CLK_SPDIF_MASK |
- CLK_PCM2_MASK |
- CLK_PCM1_MASK |
- CLK_I2S2_MASK |
- CLK_SPI2_MASK |
- CLK_SPI0_MASK);
-
- /*
- * CLK_GATE_IP_PERIS
- * Note: Keep CHIPID_APBIF ungated to ensure reading the product ID
- * register (PRO_ID) works correctly when the OS kernel determines
- * which chip it is running on.
- */
- clrbits_le32(&clk->gate_ip_peris, CLK_RTC_MASK |
- CLK_TZPC9_MASK |
- CLK_TZPC8_MASK |
- CLK_TZPC7_MASK |
- CLK_TZPC6_MASK |
- CLK_TZPC5_MASK |
- CLK_TZPC4_MASK |
- CLK_TZPC3_MASK |
- CLK_TZPC2_MASK |
- CLK_TZPC1_MASK |
- CLK_TZPC0_MASK);
-
- /* CLK_GATE_BLOCK */
- clrbits_le32(&clk->gate_block, CLK_ACP_MASK);
-
- /* CLK_GATE_IP_CDREX */
- clrbits_le32(&clk->gate_ip_cdrex, CLK_DPHY0_MASK |
- CLK_DPHY1_MASK |
- CLK_TZASC_DRBXR_MASK);
-
+ /* Not implemented for now. */
}
void clock_init_dp_clock(void)
{
- struct exynos5_clock *clk = (struct exynos5_clock *)EXYNOS5_CLOCK_BASE;
-
- /* DP clock enable */
- setbits_le32(&clk->gate_ip_disp1, CLK_GATE_DP1_ALLOW);
-
- /* We run DP at 267 Mhz */
- setbits_le32(&clk->div_disp1_0, CLK_DIV_DISP1_0_FIMD1);
+ /* Not implemented for now. */
}
-
diff --git a/src/cpu/samsung/exynos5420/setup.h b/src/cpu/samsung/exynos5420/setup.h
index 7a779ba81b..34056f3978 100644
--- a/src/cpu/samsung/exynos5420/setup.h
+++ b/src/cpu/samsung/exynos5420/setup.h
@@ -26,6 +26,8 @@ struct exynos5_dmc;
enum ddr_mode;
struct exynos5_phy_control;
+#define NOT_AVAILABLE 0
+
/* TZPC : Register Offsets */
#define TZPC0_BASE 0x10100000
#define TZPC1_BASE 0x10110000
@@ -39,34 +41,50 @@ struct exynos5_phy_control;
#define TZPC9_BASE 0x10190000
/* APLL_CON1 */
-#define APLL_CON1_VAL (0x00203800)
+#define APLL_CON1_VAL (0x0020f300)
/* MPLL_CON1 */
-#define MPLL_CON1_VAL (0x00203800)
+#define MPLL_CON1_VAL (0x0020f300)
/* CPLL_CON1 */
-#define CPLL_CON1_VAL (0x00203800)
+#define CPLL_CON1_VAL (0x0020f300)
+
+/* DPLL_CON1 */
+#define DPLL_CON1_VAL (0x0020f300)
/* GPLL_CON1 */
-#define GPLL_CON1_VAL (0x00203800)
+#define GPLL_CON1_VAL (NOT_AVAILABLE)
/* EPLL_CON1, CON2 */
#define EPLL_CON1_VAL 0x00000000
#define EPLL_CON2_VAL 0x00000080
/* VPLL_CON1, CON2 */
-#define VPLL_CON1_VAL 0x00000000
-#define VPLL_CON2_VAL 0x00000080
+#define VPLL_CON1_VAL 0x0020f300
+#define VPLL_CON2_VAL NOT_AVAILABLE
+
+/* RPLL_CON1, CON2 */
+#define RPLL_CON1_VAL 0x00000000
+#define RPLL_CON2_VAL 0x00000080
/* BPLL_CON1 */
-#define BPLL_CON1_VAL 0x00203800
+#define BPLL_CON1_VAL 0x0020f300
+
+/* SPLL_CON1 */
+#define SPLL_CON1_VAL 0x0020f300
+
+/* IPLL_CON1 */
+#define IPLL_CON1_VAL 0x00000080
+
+/* KPLL_CON1 */
+#define KPLL_CON1_VAL 0x200000
/* Set PLL */
#define set_pll(mdiv, pdiv, sdiv) (1<<31 | mdiv<<16 | pdiv<<8 | sdiv)
/* CLK_SRC_CPU */
/* 0 = MOUTAPLL, 1 = SCLKMPLL */
-#define MUX_HPM_SEL 0
+#define MUX_HPM_SEL 1
#define MUX_CPU_SEL 0
#define MUX_APLL_SEL 1
@@ -146,20 +164,11 @@ struct exynos5_phy_control;
#define DMC_CONCONTROL_TIMEOUT_LEVEL0 (0xFFF << 16)
#define DMC_CONCONTROL_DFI_INIT_START_DISABLE (0 << 28)
-/* CLK_DIV_CPU0_VAL */
-#define CLK_DIV_CPU0_VAL ((ARM2_RATIO << 28) \
- | (APLL_RATIO << 24) \
- | (PCLK_DBG_RATIO << 20) \
- | (ATB_RATIO << 16) \
- | (PERIPH_RATIO << 12) \
- | (ACP_RATIO << 8) \
- | (CPUD_RATIO << 4) \
- | (ARM_RATIO))
-
-
/* CLK_FSYS */
-#define CLK_SRC_FSYS0_VAL 0x66666
-#define CLK_DIV_FSYS0_VAL 0x0BB00000
+#define CLK_SRC_FSYS0_VAL 0x33033300
+#define CLK_DIV_FSYS0_VAL 0x0
+#define CLK_DIV_FSYS1_VAL 0x04f13c4f
+#define CLK_DIV_FSYS2_VAL 0x041d0000
/* CLK_DIV_CPU1 */
#define HPM_RATIO 0x2
@@ -191,141 +200,57 @@ struct exynos5_phy_control;
#define CLK_DIV_SYSLFT_VAL 0x00000311
/* CLK_SRC_CDREX */
-#define CLK_SRC_CDREX_VAL 0x1
+#define CLK_SRC_CDREX_VAL 0x00000001
/* CLK_DIV_CDREX */
-#define MCLK_CDREX2_RATIO 0x0
-#define ACLK_EFCON_RATIO 0x1
-#define MCLK_DPHY_RATIO 0x1
-#define MCLK_CDREX_RATIO 0x1
-#define ACLK_C2C_200_RATIO 0x1
-#define C2C_CLK_400_RATIO 0x1
-#define PCLK_CDREX_RATIO 0x1
-#define ACLK_CDREX_RATIO 0x1
-
-#define CLK_DIV_CDREX_VAL ((MCLK_DPHY_RATIO << 24) \
- | (C2C_CLK_400_RATIO << 6) \
- | (PCLK_CDREX_RATIO << 4) \
- | (ACLK_CDREX_RATIO))
-
-/* CLK_SRC_TOP0 */
-#define MUX_ACLK_300_GSCL_SEL 0x0
-#define MUX_ACLK_300_GSCL_MID_SEL 0x0
-#define MUX_ACLK_400_G3D_MID_SEL 0x0
-#define MUX_ACLK_333_SEL 0x0
-#define MUX_ACLK_300_DISP1_SEL 0x0
-#define MUX_ACLK_300_DISP1_MID_SEL 0x0
-#define MUX_ACLK_200_SEL 0x0
-#define MUX_ACLK_166_SEL 0x0
-#define CLK_SRC_TOP0_VAL ((MUX_ACLK_300_GSCL_SEL << 25) \
- | (MUX_ACLK_300_GSCL_MID_SEL << 24) \
- | (MUX_ACLK_400_G3D_MID_SEL << 20) \
- | (MUX_ACLK_333_SEL << 16) \
- | (MUX_ACLK_300_DISP1_SEL << 15) \
- | (MUX_ACLK_300_DISP1_MID_SEL << 14) \
- | (MUX_ACLK_200_SEL << 12) \
- | (MUX_ACLK_166_SEL << 8))
-
-/* CLK_SRC_TOP1 */
-#define MUX_ACLK_400_G3D_SEL 0x1
-#define MUX_ACLK_400_ISP_SEL 0x0
-#define MUX_ACLK_400_IOP_SEL 0x0
-#define MUX_ACLK_MIPI_HSI_TXBASE_SEL 0x0
-#define MUX_ACLK_300_GSCL_MID1_SEL 0x0
-#define MUX_ACLK_300_DISP1_MID1_SEL 0x0
-#define CLK_SRC_TOP1_VAL ((MUX_ACLK_400_G3D_SEL << 28) \
- |(MUX_ACLK_400_ISP_SEL << 24) \
- |(MUX_ACLK_400_IOP_SEL << 20) \
- |(MUX_ACLK_MIPI_HSI_TXBASE_SEL << 16) \
- |(MUX_ACLK_300_GSCL_MID1_SEL << 12) \
- |(MUX_ACLK_300_DISP1_MID1_SEL << 8))
-
-/* CLK_SRC_TOP2 */
-#define MUX_GPLL_SEL 0x1
-#define MUX_BPLL_USER_SEL 0x0
-#define MUX_MPLL_USER_SEL 0x0
-#define MUX_VPLL_SEL 0x1
-#define MUX_EPLL_SEL 0x1
-#define MUX_CPLL_SEL 0x1
-#define VPLLSRC_SEL 0x0
-#define CLK_SRC_TOP2_VAL ((MUX_GPLL_SEL << 28) \
- | (MUX_BPLL_USER_SEL << 24) \
- | (MUX_MPLL_USER_SEL << 20) \
- | (MUX_VPLL_SEL << 16) \
- | (MUX_EPLL_SEL << 12) \
- | (MUX_CPLL_SEL << 8) \
- | (VPLLSRC_SEL))
-/* CLK_SRC_TOP3 */
-#define MUX_ACLK_333_SUB_SEL 0x1
-#define MUX_ACLK_400_SUB_SEL 0x1
-#define MUX_ACLK_266_ISP_SUB_SEL 0x1
-#define MUX_ACLK_266_GPS_SUB_SEL 0x0
-#define MUX_ACLK_300_GSCL_SUB_SEL 0x1
-#define MUX_ACLK_266_GSCL_SUB_SEL 0x1
-#define MUX_ACLK_300_DISP1_SUB_SEL 0x1
-#define MUX_ACLK_200_DISP1_SUB_SEL 0x1
-#define CLK_SRC_TOP3_VAL ((MUX_ACLK_333_SUB_SEL << 24) \
- | (MUX_ACLK_400_SUB_SEL << 20) \
- | (MUX_ACLK_266_ISP_SUB_SEL << 16) \
- | (MUX_ACLK_266_GPS_SUB_SEL << 12) \
- | (MUX_ACLK_300_GSCL_SUB_SEL << 10) \
- | (MUX_ACLK_266_GSCL_SUB_SEL << 8) \
- | (MUX_ACLK_300_DISP1_SUB_SEL << 6) \
- | (MUX_ACLK_200_DISP1_SUB_SEL << 4))
-
-/* CLK_DIV_TOP0 */
-#define ACLK_300_DISP1_RATIO 0x2
-#define ACLK_400_G3D_RATIO 0x0
-#define ACLK_333_RATIO 0x0
-#define ACLK_266_RATIO 0x2
-#define ACLK_200_RATIO 0x3
-#define ACLK_166_RATIO 0x1
-#define ACLK_133_RATIO 0x1
-#define ACLK_66_RATIO 0x5
-
-#define CLK_DIV_TOP0_VAL ((ACLK_300_DISP1_RATIO << 28) \
- | (ACLK_400_G3D_RATIO << 24) \
- | (ACLK_333_RATIO << 20) \
- | (ACLK_266_RATIO << 16) \
- | (ACLK_200_RATIO << 12) \
- | (ACLK_166_RATIO << 8) \
- | (ACLK_133_RATIO << 4) \
- | (ACLK_66_RATIO))
-
-/* CLK_DIV_TOP1 */
-#define ACLK_MIPI_HSI_TX_BASE_RATIO 0x3
-#define ACLK_66_PRE_RATIO 0x1
-#define ACLK_400_ISP_RATIO 0x1
-#define ACLK_400_IOP_RATIO 0x1
-#define ACLK_300_GSCL_RATIO 0x2
-
-#define CLK_DIV_TOP1_VAL ((ACLK_MIPI_HSI_TX_BASE_RATIO << 28) \
- | (ACLK_66_PRE_RATIO << 24) \
- | (ACLK_400_ISP_RATIO << 20) \
- | (ACLK_400_IOP_RATIO << 16) \
- | (ACLK_300_GSCL_RATIO << 12))
-
-/* APLL_LOCK */
-#define APLL_LOCK_VAL (0x546)
-/* MPLL_LOCK */
-#define MPLL_LOCK_VAL (0x546)
-/* CPLL_LOCK */
-#define CPLL_LOCK_VAL (0x546)
-/* GPLL_LOCK */
-#define GPLL_LOCK_VAL (0x546)
-/* EPLL_LOCK */
-#define EPLL_LOCK_VAL (0x3A98)
-/* VPLL_LOCK */
-#define VPLL_LOCK_VAL (0x3A98)
-/* BPLL_LOCK */
-#define BPLL_LOCK_VAL (0x546)
-
-#define MUX_MCLK_CDREX_SEL (1 << 4)
-#define MUX_MCLK_DPHY_SEL (1 << 8)
+#define CLK_DIV_CDREX0_VAL 0x30010100
+#define CLK_DIV_CDREX1_VAL 0x300
+
+#define CLK_DIV_CDREX_VAL 0x17010100
+
+/* CLK_DIV_CPU0_VAL */
+#define CLK_DIV_CPU0_VAL 0x01440020
+
+/* CLK_SRC_TOP */
+#define CLK_SRC_TOP0_VAL 0x12221222
+#define CLK_SRC_TOP1_VAL 0x00100200
+#define CLK_SRC_TOP2_VAL 0x11101000
+#define CLK_SRC_TOP3_VAL 0x11111111
+#define CLK_SRC_TOP4_VAL 0x11110111
+#define CLK_SRC_TOP5_VAL 0x11111100
+#define CLK_SRC_TOP7_VAL 0x00022200
+
+/* CLK_DIV_TOP */
+#define CLK_DIV_TOP0_VAL 0x23712311
+#define CLK_DIV_TOP1_VAL 0x13100B00
+#define CLK_DIV_TOP2_VAL 0x11101100
+
+/* APLL_LOCK */
+#define APLL_LOCK_VAL (0x320)
+/* MPLL_LOCK */
+#define MPLL_LOCK_VAL (0x258)
+/* BPLL_LOCK */
+#define BPLL_LOCK_VAL (0x258)
+/* CPLL_LOCK */
+#define CPLL_LOCK_VAL (0x190)
+/* DPLL_LOCK */
+#define DPLL_LOCK_VAL (0x190)
+/* GPLL_LOCK */
+#define GPLL_LOCK_VAL NOT_AVAILABLE
+/* IPLL_LOCK */
+#define IPLL_LOCK_VAL (0x320)
+/* KPLL_LOCK */
+#define KPLL_LOCK_VAL (0x258)
+/* SPLL_LOCK */
+#define SPLL_LOCK_VAL (0x320)
+/* RPLL_LOCK */
+#define RPLL_LOCK_VAL (0x2328)
+/* EPLL_LOCK */
+#define EPLL_LOCK_VAL (0x2328)
+/* VPLL_LOCK */
+#define VPLL_LOCK_VAL (0x258)
#define MUX_APLL_SEL_MASK (1 << 0)
-#define MUX_MPLL_FOUT_SEL (1 << 4)
-#define MUX_BPLL_FOUT_SEL (1 << 0)
#define MUX_MPLL_SEL_MASK (1 << 8)
#define MPLL_SEL_MOUT_MPLLFOUT (2 << 8)
#define MUX_CPLL_SEL_MASK (1 << 8)
@@ -335,6 +260,7 @@ struct exynos5_phy_control;
#define MUX_BPLL_SEL_MASK (1 << 0)
#define MUX_HPM_SEL_MASK (1 << 20)
#define HPM_SEL_SCLK_MPLL (1 << 21)
+#define PLL_LOCKED (1 << 29)
#define APLL_CON0_LOCKED (1 << 29)
#define MPLL_CON0_LOCKED (1 << 29)
#define BPLL_CON0_LOCKED (1 << 29)
@@ -345,33 +271,75 @@ struct exynos5_phy_control;
#define CLK_REG_DISABLE 0x0
#define TOP2_VAL 0x0110000
+/* CLK_SRC_LEX */
+#define CLK_SRC_LEX_VAL 0x0
+
+/* CLK_DIV_LEX */
+#define CLK_DIV_LEX_VAL 0x10
+
+/* CLK_DIV_R0X */
+#define CLK_DIV_R0X_VAL 0x10
+
+/* CLK_DIV_L0X */
+#define CLK_DIV_R1X_VAL 0x10
+
+/* CLK_DIV_ISP2 */
+#define CLK_DIV_ISP2_VAL 0x1
+
+/* CLK_SRC_KFC */
+#define SRC_KFC_HPM_SEL (1 << 15)
+
+/* CLK_SRC_KFC */
+#define CLK_SRC_KFC_VAL 0x00008001
+
+/* CLK_DIV_KFC */
+#define CLK_DIV_KFC_VAL 0x03300110
+
+/* CLK_DIV2_RATIO */
+#define CLK_DIV2_RATIO 0x10111150
+
+/* CLK_DIV4_RATIO */
+#define CLK_DIV4_RATIO 0x00000003
+
+/* CLK_DIV_G2D */
+#define CLK_DIV_G2D 0x00000010
+
/* CLK_SRC_PERIC0 */
-#define PWM_SEL 6
-#define UART3_SEL 6
-#define UART2_SEL 6
-#define UART1_SEL 6
-#define UART0_SEL 6
-/* SRC_CLOCK = SCLK_MPLL */
-#define CLK_SRC_PERIC0_VAL ((PWM_SEL << 24) \
- | (UART3_SEL << 12) \
- | (UART2_SEL << 8) \
- | (UART1_SEL << 4) \
- | (UART0_SEL))
+#define SPDIF_SEL 1
+#define PWM_SEL 3
+#define UART4_SEL 3
+#define UART3_SEL 3
+#define UART2_SEL 3
+#define UART1_SEL 3
+#define UART0_SEL 3
+/* SRC_CLOCK = SCLK_RPLL */
+#define CLK_SRC_PERIC0_VAL ((SPDIF_SEL << 28) \
+ | (PWM_SEL << 24) \
+ | (UART4_SEL << 20) \
+ | (UART3_SEL << 16) \
+ | (UART2_SEL << 12) \
+ | (UART1_SEL << 8) \
+ | (UART0_SEL << 4))
/* CLK_SRC_PERIC1 */
-/* SRC_CLOCK = SCLK_MPLL */
+/* SRC_CLOCK = SCLK_EPLL */
#define SPI0_SEL 6
#define SPI1_SEL 6
#define SPI2_SEL 6
-#define CLK_SRC_PERIC1_VAL ((SPI2_SEL << 24) \
- | (SPI1_SEL << 20) \
- | (SPI0_SEL << 16))
-
-/* SCLK_SRC_ISP - set SPI0/1 to 6 = SCLK_MPLL_USER */
-#define SPI0_ISP_SEL 6
-#define SPI1_ISP_SEL 6
-#define SCLK_SRC_ISP_VAL (SPI1_ISP_SEL << 4) \
- | (SPI0_ISP_SEL << 0)
+#define AUDIO0_SEL 6
+#define AUDIO1_SEL 6
+#define AUDIO2_SEL 6
+#define CLK_SRC_PERIC1_VAL ((SPI2_SEL << 28) \
+ | (SPI1_SEL << 24) \
+ | (SPI0_SEL << 20) \
+ | (AUDIO2_SEL << 16) \
+ | (AUDIO2_SEL << 12) \
+ | (AUDIO2_SEL << 8))
+
+/* CLK_SRC_ISP */
+#define CLK_SRC_ISP_VAL 0x33366000
+#define CLK_DIV_ISP0_VAL 0x13131300
+#define CLK_DIV_ISP1_VAL 0xbb110202
/* SCLK_DIV_ISP - set SPI0/1 to 0xf = divide by 16 */
#define SPI0_ISP_RATIO 0xf
@@ -380,32 +348,50 @@ struct exynos5_phy_control;
| (SPI0_ISP_RATIO << 0)
/* CLK_DIV_PERIL0 */
-#define UART5_RATIO 7
-#define UART4_RATIO 7
-#define UART3_RATIO 7
-#define UART2_RATIO 7
-#define UART1_RATIO 7
-#define UART0_RATIO 7
-
-#define CLK_DIV_PERIC0_VAL ((UART3_RATIO << 12) \
- | (UART2_RATIO << 8) \
- | (UART1_RATIO << 4) \
- | (UART0_RATIO))
+#define PWM_RATIO 8
+#define UART4_RATIO 9
+#define UART3_RATIO 9
+#define UART2_RATIO 9
+#define UART1_RATIO 9
+#define UART0_RATIO 9
+
+#define CLK_DIV_PERIC0_VAL ((PWM_RATIO << 28) \
+ | (UART4_RATIO << 24) \
+ | (UART3_RATIO << 20) \
+ | (UART2_RATIO << 16) \
+ | (UART1_RATIO << 12) \
+ | (UART0_RATIO << 8))
+
/* CLK_DIV_PERIC1 */
-#define SPI1_RATIO 0x7
-#define SPI0_RATIO 0xf
-#define SPI1_SUB_RATIO 0x0
-#define SPI0_SUB_RATIO 0x0
-#define CLK_DIV_PERIC1_VAL ((SPI1_SUB_RATIO << 24) \
- | ((SPI1_RATIO << 16) \
- | (SPI0_SUB_RATIO << 8) \
- | (SPI0_RATIO << 0)))
+#define SPI2_RATIO 0x1
+#define SPI1_RATIO 0x1
+#define SPI0_RATIO 0x1
+#define CLK_DIV_PERIC1_VAL ((SPI2_RATIO << 28) \
+ | (SPI1_RATIO << 24) \
+ | (SPI0_RATIO << 20))
/* CLK_DIV_PERIC2 */
-#define SPI2_RATIO 0xf
-#define SPI2_SUB_RATIO 0x0
-#define CLK_DIV_PERIC2_VAL ((SPI2_SUB_RATIO << 8) \
- | (SPI2_RATIO << 0))
+#define PCM2_RATIO 0x3
+#define PCM1_RATIO 0x3
+#define CLK_DIV_PERIC2_VAL ((PCM2_RATIO << 24) \
+ | (PCM1_RATIO << 16))
+
+/* CLK_DIV_PERIC3 */
+#define AUDIO2_RATIO 0x5
+#define AUDIO1_RATIO 0x5
+#define AUDIO0_RATIO 0x5
+#define CLK_DIV_PERIC3_VAL ((AUDIO2_RATIO << 28) \
+ | (AUDIO1_RATIO << 24) \
+ | (AUDIO0_RATIO << 20))
+
+/* CLK_DIV_PERIC4 */
+#define SPI2_PRE_RATIO 0x2
+#define SPI1_PRE_RATIO 0x2
+#define SPI0_PRE_RATIO 0x2
+#define CLK_DIV_PERIC4_VAL ((SPI2_PRE_RATIO << 24) \
+ | (SPI1_PRE_RATIO << 16) \
+ | (SPI0_PRE_RATIO << 8))
+
/* CLK_DIV_FSYS2 */
#define MMC2_RATIO_MASK 0xf
#define MMC2_RATIO_VAL 0x3
@@ -435,17 +421,12 @@ struct exynos5_phy_control;
/* CLK_DIV_L0X */
#define CLK_DIV_R1X_VAL 0x10
-/* CLK_DIV_ISP0 */
-#define CLK_DIV_ISP0_VAL 0x31
-
-/* CLK_DIV_ISP1 */
-#define CLK_DIV_ISP1_VAL 0x0
-
/* CLK_DIV_ISP2 */
#define CLK_DIV_ISP2_VAL 0x1
/* CLK_SRC_DISP1_0 */
-#define CLK_SRC_DISP1_0_VAL 0x6
+#define CLK_SRC_DISP1_0_VAL 0x10666600
+#define CLK_DIV_DISP1_0_VAL 0x01050210
/*
* DIV_DISP1_0
@@ -538,6 +519,12 @@ struct exynos5_phy_control;
#define CLK_MIXER_MASK (1 << 5)
#define CLK_DSIM1_MASK (1 << 3)
+/* AUDIO CLK SEL */
+#define AUDIO0_SEL_EPLL (0x6 << 28)
+#define AUDIO0_RATIO 0x5
+#define PCM0_RATIO 0x3
+#define DIV_MAU_VAL (PCM0_RATIO << 24 | AUDIO0_RATIO << 20)
+
/* CLK_GATE_IP_GEN */
#define CLK_SMMUMDMA1_MASK (1 << 9)
#define CLK_SMMUJPEG_MASK (1 << 7)