diff options
| author | Stefan Reinauer <reinauer@chromium.org> | 2013-09-09 14:37:03 -0700 |
|---|---|---|
| committer | Isaac Christensen <isaac.christensen@se-eng.com> | 2014-08-14 01:43:57 +0200 |
| commit | 8f993784ef71f451995dd67fc709b88399c8a7e9 (patch) | |
| tree | d2cbe6361bb6e1c9dcc4ead2273cc66007a06ceb /src/cpu/samsung/exynos5420 | |
| parent | fa938c7508627c0dfcf03960957ef8631fc53f02 (diff) | |
ARMv7/Exynos: Fix memory location assumptions
This patch cleans out a lot of unused variables in the
ARM Kconfig files and introduces CONFIG_RAMSTAGE_BASE
which is similar to CONFIG_RAMBASE on x86.
This gets rid of the hard coded assumption that on ARM
coreboot is always executed at the lowest DRAM address.
But in fact, this might not be true because we might want
coreboot to live at the end of RAM, or in SRAM
Change-Id: I03e992645f9eb730e39a521aa21f702959311f74
Signed-off-by: Stefan Reinauer <reinauer@google.com>
Reviewed-on: https://chromium-review.googlesource.com/168645
Reviewed-by: David Hendrix <dhendrix@chromium.org>
Tested-by: David Hendrix <dhendrix@chromium.org>
(cherry picked from commit 15b87892eb2d5e27759c49dc6c8c7e626f651d77)
Signed-off-by: Isaac Christensen <isaac.christensen@se-eng.com>
Reviewed-on: http://review.coreboot.org/6634
Tested-by: build bot (Jenkins)
Reviewed-by: Patrick Georgi <patrick@georgi-clan.de>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Diffstat (limited to 'src/cpu/samsung/exynos5420')
| -rw-r--r-- | src/cpu/samsung/exynos5420/Kconfig | 20 |
1 files changed, 5 insertions, 15 deletions
diff --git a/src/cpu/samsung/exynos5420/Kconfig b/src/cpu/samsung/exynos5420/Kconfig index 1379de1255..460b1771a7 100644 --- a/src/cpu/samsung/exynos5420/Kconfig +++ b/src/cpu/samsung/exynos5420/Kconfig @@ -40,6 +40,9 @@ config CBFS_ROM_OFFSET hex "offset of CBFS data in ROM" default 0x0A000 +config SYS_SDRAM_BASE + hex + default 0x20000000 # Example SRAM/iRAM map for Exynos5420 platform: # @@ -63,9 +66,9 @@ config ROMSTAGE_BASE hex default 0x02030000 -config ROMSTAGE_SIZE +config RAMSTAGE_BASE hex - default 0x20000 + default SYS_SDRAM_BASE # Stack may reside in either IRAM or DRAM. We will define it to live # at the top of IRAM for now. @@ -90,11 +93,6 @@ config STACK_BOTTOM hex default 0x0206f000 -# The romstage stack must be large enough to contain the lzma buffer -config ROMSTAGE_STACK_SIZE - hex - default 0x4000 - # STACK_SIZE is for the ramstage core and thread stacks. # It must be a power of 2, to make the cpu_info computation work, # and cpu_info needs to work to make SMP startup and threads work. @@ -116,12 +114,4 @@ config TTB_BUFFER hex "memory address of the TTB buffer" default 0x02058000 -config TTB_SIZE - hex "size of the TTB buffer" - default 0x4000 - -config SYS_SDRAM_BASE - hex - default 0x20000000 - endif |