diff options
| author | Julius Werner <jwerner@chromium.org> | 2013-09-03 15:07:31 -0700 |
|---|---|---|
| committer | Isaac Christensen <isaac.christensen@se-eng.com> | 2014-08-18 19:02:41 +0200 |
| commit | 68aef1169239cc5d33fb36f05cd32d7e062b7743 (patch) | |
| tree | 3a1436c1e348fbd6d9020ac578c8aa31cf00d86b /src/cpu/samsung/exynos5420/usb.h | |
| parent | 9125d88596181549f9cd7988c6dd748d54b299ee (diff) | |
exynos5: Implement support for USB 3.0 DRD PHYs/controllers
This patch adds support for the DesignWare3 USB 3.0 DRD controller and
PHY to the Exynos5250 and Exynos5420 CPUs. It also adds code to the
Google Snow and Pit boards to turn these controllers on where
applicable.
Change-Id: Idcca627363a69f1d65402e1acb9a62b439f077ff
Signed-off-by: Julius Werner <jwerner@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/169452
Reviewed-by: Stefan Reinauer <reinauer@google.com>
(cherry picked from commit e9809ae12ef8b8bd6cd61d3f604cb9e4718cf7eb)
Signed-off-by: Isaac Christensen <isaac.christensen@se-eng.com>
Reviewed-on: http://review.coreboot.org/6642
Tested-by: build bot (Jenkins)
Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
Diffstat (limited to 'src/cpu/samsung/exynos5420/usb.h')
| -rw-r--r-- | src/cpu/samsung/exynos5420/usb.h | 84 |
1 files changed, 80 insertions, 4 deletions
diff --git a/src/cpu/samsung/exynos5420/usb.h b/src/cpu/samsung/exynos5420/usb.h index 7eb317c68e..b3c2a33fd6 100644 --- a/src/cpu/samsung/exynos5420/usb.h +++ b/src/cpu/samsung/exynos5420/usb.h @@ -45,24 +45,100 @@ struct exynos5_usb_host_phy { uint32_t usbphyctrl0; uint32_t usbphytune0; - uint32_t reserved1[2]; + uint8_t reserved1[8]; uint32_t hsicphyctrl1; uint32_t hsicphytune1; - uint32_t reserved2[2]; + uint8_t reserved2[8]; uint32_t hsicphyctrl2; uint32_t hsicphytune2; - uint32_t reserved3[2]; + uint8_t reserved3[8]; uint32_t ehcictrl; uint32_t ohcictrl; uint32_t usbotgsys; - uint32_t reserved4; + uint8_t reserved4[4]; uint32_t usbotgtune; }; static struct exynos5_usb_host_phy * const exynos_usb_host_phy = (void *)EXYNOS5_USB_HOST_PHY_BASE; +struct exynos5_usb_drd_phy { + uint8_t reserved1[4]; + uint32_t linksystem; + uint32_t utmi; + uint32_t pipe; + uint32_t clkrst; + uint32_t reg0; + uint32_t reg1; + uint32_t param0; + uint32_t param1; + uint32_t term; + uint32_t test; + uint32_t adp; + uint32_t utmiclksel; + uint32_t resume; + uint8_t reserved2[8]; + uint32_t linkhcbelt; + uint32_t linkport; +}; + +static struct exynos5_usb_drd_phy * const exynos_usb_drd0_phy = + (void *)EXYNOS5420_USB_DRD0_PHY_BASE; +static struct exynos5_usb_drd_phy * const exynos_usb_drd1_phy = + (void *)EXYNOS5420_USB_DRD1_PHY_BASE; + +struct exynos5_usb_drd_dwc3 { + uint32_t sbuscfg0; + uint32_t sbuscfg1; + uint32_t txthrcfg; + uint32_t rxthrcfg; + uint32_t ctl; + uint32_t evten; + uint32_t sts; + uint8_t reserved0[4]; + uint32_t snpsid; + uint32_t gpio; + uint32_t uid; + uint32_t uctl; + uint64_t buserraddr; + uint64_t prtbimap; + uint8_t reserved1[32]; + uint32_t dbgfifospace; + uint32_t dbgltssm; + uint32_t dbglnmcc; + uint32_t dbgbmu; + uint32_t dbglspmux; + uint32_t dbglsp; + uint32_t dbgepinfo0; + uint32_t dbgepinfo1; + uint64_t prtbimap_hs; + uint64_t prtbimap_fs; + uint8_t reserved2[112]; + uint32_t usb2phycfg; + uint8_t reserved3[60]; + uint32_t usb2i2cctl; + uint8_t reserved4[60]; + uint32_t usb2phyacc; + uint8_t reserved5[60]; + uint32_t usb3pipectl; + uint8_t reserved6[60]; +}; + +static struct exynos5_usb_drd_dwc3 * const exynos_usb_drd0_dwc3 = + (void *)EXYNOS5420_USB_DRD0_DWC3_BASE; +static struct exynos5_usb_drd_dwc3 * const exynos_usb_drd1_dwc3 = + (void *)EXYNOS5420_USB_DRD1_DWC3_BASE; + /* Leave hsic_gpio at 0 to not enable HSIC. */ void setup_usb_host_phy(int hsic_gpio); +void setup_usb_drd0_phy(void); +void setup_usb_drd1_phy(void); + +/* Call reset_ before setup_, ensure at least 100ms pass in between. */ +void reset_usb_drd0_dwc3(void); +void reset_usb_drd1_dwc3(void); +void setup_usb_drd0_dwc3(void); +void setup_usb_drd1_dwc3(void); + #endif |