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authorJulius Werner <jwerner@chromium.org>2013-08-29 14:17:36 -0700
committerIsaac Christensen <isaac.christensen@se-eng.com>2014-08-14 01:43:11 +0200
commitfa938c7508627c0dfcf03960957ef8631fc53f02 (patch)
tree369a6f41d6a4a152ec933b08e869d6bb527adac4 /src/cpu/samsung/exynos5420/usb.c
parent755615a12310469b34fc4804bcf2622eb587949c (diff)
exynos5: Refactor crazy old U-Boot base address macros away
All this samsung_get_base_address_of_device_with_a_really_long_name() boilerplate makes my eyes bleed... I think there are so much cleaner ways to do this. Unfortunately changing this ends up touching nearly every Exynos5 file, but I hope you agree that it's worth it (and the sooner we get it over with, the better... I can't bring myself to make another device fit into that ugly scheme). This also removes the redundant EXYNOS5 base address definitions from the 5420 directory when there are EXYNOS5420 ones, to avoid complete confusion. The new scheme tries to use EXYNOS5 for base addresses and exynos5 for types that are common between the two processors, and EXYNOS5420/exynos5420 for things that have changes (although I probably didn't catch all differences). Change-Id: I87e58434490ed55a9bbe743af1f9bf2520dec13f Signed-off-by: Julius Werner <jwerner@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/167579 Reviewed-by: Stefan Reinauer <reinauer@google.com> Reviewed-by: David Hendricks <dhendrix@chromium.org> Reviewed-by: ron minnich <rminnich@chromium.org> (cherry picked from commit 66c87693352c248eec029c1ce83fb295059e6b5b) Signed-off-by: Isaac Christensen <isaac.christensen@se-eng.com> Reviewed-on: http://review.coreboot.org/6632 Tested-by: build bot (Jenkins) Reviewed-by: Ronald G. Minnich <rminnich@gmail.com> Reviewed-by: Edward O'Callaghan <eocallaghan@alterapraxis.com> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Diffstat (limited to 'src/cpu/samsung/exynos5420/usb.c')
-rw-r--r--src/cpu/samsung/exynos5420/usb.c25
1 files changed, 12 insertions, 13 deletions
diff --git a/src/cpu/samsung/exynos5420/usb.c b/src/cpu/samsung/exynos5420/usb.c
index 9e990a1137..521ea4da5a 100644
--- a/src/cpu/samsung/exynos5420/usb.c
+++ b/src/cpu/samsung/exynos5420/usb.c
@@ -22,7 +22,6 @@
#include <arch/io.h>
#include <console/console.h>
#include <device/device.h>
-#include "cpu.h"
#include "gpio.h"
#include "power.h"
#include "sysreg.h"
@@ -31,17 +30,15 @@
void setup_usb_host_phy(int hsic_gpio)
{
unsigned int hostphy_ctrl0;
- struct exynos5_sysreg *sysreg = samsung_get_base_sysreg();
- struct exynos5_power *power = samsung_get_base_power();
- struct exynos5_usb_host_phy *phy = samsung_get_base_usb_host_phy();
- setbits_le32(&sysreg->usb20_phy_cfg, USB20_PHY_CFG_EN);
- setbits_le32(&power->usb_host_phy_ctrl, POWER_USB_HOST_PHY_CTRL_EN);
+ setbits_le32(&exynos_sysreg->usb20_phy_cfg, USB20_PHY_CFG_EN);
+ setbits_le32(&exynos_power->usb_host_phy_ctrl,
+ POWER_USB_HOST_PHY_CTRL_EN);
printk(BIOS_DEBUG, "Powering up USB HOST PHY (%s HSIC)\n",
hsic_gpio ? "with" : "without");
- hostphy_ctrl0 = readl(&phy->usbphyctrl0);
+ hostphy_ctrl0 = readl(&exynos_usb_host_phy->usbphyctrl0);
hostphy_ctrl0 &= ~(HOST_CTRL0_FSEL_MASK |
HOST_CTRL0_COMMONON_N |
/* HOST Phy setting */
@@ -55,15 +52,15 @@ void setup_usb_host_phy(int hsic_gpio)
/* HOST Phy setting */
HOST_CTRL0_LINKSWRST |
HOST_CTRL0_UTMISWRST);
- writel(hostphy_ctrl0, &phy->usbphyctrl0);
+ writel(hostphy_ctrl0, &exynos_usb_host_phy->usbphyctrl0);
udelay(10);
- clrbits_le32(&phy->usbphyctrl0,
+ clrbits_le32(&exynos_usb_host_phy->usbphyctrl0,
HOST_CTRL0_LINKSWRST |
HOST_CTRL0_UTMISWRST);
udelay(20);
/* EHCI Ctrl setting */
- setbits_le32(&phy->ehcictrl,
+ setbits_le32(&exynos_usb_host_phy->ehcictrl,
EHCICTRL_ENAINCRXALIGN |
EHCICTRL_ENAINCR4 |
EHCICTRL_ENAINCR8 |
@@ -76,13 +73,15 @@ void setup_usb_host_phy(int hsic_gpio)
gpio_direction_output(hsic_gpio, 1);
udelay(5000);
- clrbits_le32(&phy->hsicphyctrl1,
+ clrbits_le32(&exynos_usb_host_phy->hsicphyctrl1,
HOST_CTRL0_SIDDQ |
HOST_CTRL0_FORCESLEEP |
HOST_CTRL0_FORCESUSPEND);
- setbits_le32(&phy->hsicphyctrl1, HOST_CTRL0_PHYSWRST);
+ setbits_le32(&exynos_usb_host_phy->hsicphyctrl1,
+ HOST_CTRL0_PHYSWRST);
udelay(10);
- clrbits_le32(&phy->hsicphyctrl1, HOST_CTRL0_PHYSWRST);
+ clrbits_le32(&exynos_usb_host_phy->hsicphyctrl1,
+ HOST_CTRL0_PHYSWRST);
}
/* At this point we need to wait for 50ms before talking to