diff options
| author | Gabe Black <gabeblack@google.com> | 2013-06-24 03:14:41 -0700 |
|---|---|---|
| committer | Stefan Reinauer <stefan.reinauer@coreboot.org> | 2013-07-10 23:00:41 +0200 |
| commit | 7c2ae7ae53ac2bc4dadc55ba5445d0556ee32251 (patch) | |
| tree | a2fe4a7c3e680763b08a7ddbe071d7270f785713 /src/cpu/samsung/exynos5420/setup.h | |
| parent | 04d6e01d43626383fb80936ef1237df67cf23ca1 (diff) | |
exynos5420: Clock the mmc blocks off of the mpll.
The exynos manual suggests hooking the mmc ip blocks to the mpll. They had
been set to use a different pll. This changes them over and modifies the
divider so that the frequency stays the same.
Change-Id: I85103388d6cc2c63d1ca004654fc08fcc8929962
Signed-off-by: Gabe Black <gabeblack@chromium.org>
Reviewed-on: http://review.coreboot.org/3703
Tested-by: build bot (Jenkins)
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
Diffstat (limited to 'src/cpu/samsung/exynos5420/setup.h')
| -rw-r--r-- | src/cpu/samsung/exynos5420/setup.h | 4 |
1 files changed, 2 insertions, 2 deletions
diff --git a/src/cpu/samsung/exynos5420/setup.h b/src/cpu/samsung/exynos5420/setup.h index 7d63772832..e89ed8eee4 100644 --- a/src/cpu/samsung/exynos5420/setup.h +++ b/src/cpu/samsung/exynos5420/setup.h @@ -222,7 +222,7 @@ struct exynos5_phy_control; #define CLK_DIV_CPU0_VAL 0x01440020 /* CLK_SRC_TOP */ -#define CLK_SRC_TOP0_VAL 0x12221222 +#define CLK_SRC_TOP0_VAL 0x12222222 #define CLK_SRC_TOP1_VAL 0x00100200 #define CLK_SRC_TOP2_VAL 0x11101000 #define CLK_SRC_TOP3_VAL 0x11111111 @@ -231,7 +231,7 @@ struct exynos5_phy_control; #define CLK_SRC_TOP7_VAL 0x00022200 /* CLK_DIV_TOP */ -#define CLK_DIV_TOP0_VAL 0x23712311 +#define CLK_DIV_TOP0_VAL 0x23713311 #define CLK_DIV_TOP1_VAL 0x13100B00 #define CLK_DIV_TOP2_VAL 0x11101100 |