diff options
author | David Hendricks <dhendrix@chromium.org> | 2013-08-29 13:12:56 -0700 |
---|---|---|
committer | Isaac Christensen <isaac.christensen@se-eng.com> | 2014-08-12 22:20:23 +0200 |
commit | 5a0fdb4565dc6baf89155268dd0f52e6885197d8 (patch) | |
tree | 9e29218f8c95cf5321f39067c798ae405532a973 /src/cpu/samsung/exynos5420/dmc.h | |
parent | 122b6d6ce694cd55087b4956780b2bbde8ccc6fe (diff) |
exynos5420: minor clean-up memory related stuff
This cleans up a few minor things (mostly #defines) of the memory code
for exynos5420, pit, and kirby. Specifically:
- CONCONTROL.empty is read-only, so don't try to set it and also
get rid of the unneeded DMC_CONCONTROL_EMPTY_ENABLE #define.
- MEMBASECONFIG* overlaps members of the mem_timings struct and
are mainboard-dependent anyway, so get rid of 'em.
- DMC_MEMCONTROL_TP_DISABLE corresponds to a reserved bit. It may
have been deprecated.
- Same with TIMING* #defines.
- Clarify DDR_MODE_* usage and use mem->mem_type when appropriate.
Signed-off-by: David Hendricks <dhendrix@chromium.org>
Change-Id: Ideb21efcc97b24f7e115e90051c20daef4480f17
Reviewed-on: https://chromium-review.googlesource.com/167500
Commit-Queue: David Hendricks <dhendrix@chromium.org>
Tested-by: David Hendricks <dhendrix@chromium.org>
Reviewed-by: ron minnich <rminnich@chromium.org>
(cherry picked from commit 650dba32cb217414c422907398f68e784e5720e8)
Signed-off-by: Isaac Christensen <isaac.christensen@se-eng.com>
Reviewed-on: http://review.coreboot.org/6614
Tested-by: build bot (Jenkins)
Reviewed-by: David Hendricks <dhendrix@chromium.org>
Diffstat (limited to 'src/cpu/samsung/exynos5420/dmc.h')
-rw-r--r-- | src/cpu/samsung/exynos5420/dmc.h | 9 |
1 files changed, 5 insertions, 4 deletions
diff --git a/src/cpu/samsung/exynos5420/dmc.h b/src/cpu/samsung/exynos5420/dmc.h index 89fac429b7..1a6adca6f9 100644 --- a/src/cpu/samsung/exynos5420/dmc.h +++ b/src/cpu/samsung/exynos5420/dmc.h @@ -259,10 +259,11 @@ struct exynos5_tzasc { } __attribute__((packed)); enum ddr_mode { - DDR_MODE_DDR2, - DDR_MODE_DDR3, - DDR_MODE_LPDDR2, - DDR_MODE_LPDDR3, + /* This is in order of ctrl_ddr_mode values. Do not change. */ + DDR_MODE_DDR2 = 0x0, + DDR_MODE_DDR3 = 0x1, + DDR_MODE_LPDDR2 = 0x2, + DDR_MODE_LPDDR3 = 0x3, DDR_MODE_COUNT, }; |