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authorEdward O'Callaghan <eocallaghan@alterapraxis.com>2014-07-08 01:53:24 +1000
committerEdward O'Callaghan <eocallaghan@alterapraxis.com>2014-07-11 08:39:07 +0200
commit7116ac803736345cc7c7b73ac435efa50c4cd2b0 (patch)
tree64b7190ef4e61ba2e17a88c50e92c076c3aa2d19 /src/cpu/samsung/exynos5420/clock.c
parentc805e62f9dd5e1b11906101845abd36b049e7dc3 (diff)
src: Make use of 'CEIL_DIV(a, b)' macro across tree
The objective here is to tighten coreboot up a bit by not repeating common helpers. This makes the code base more consistent and unified/tight. Change-Id: Ia163eae68b4a84a00ed118125e70308fab1cea0c Signed-off-by: Edward O'Callaghan <eocallaghan@alterapraxis.com> Reviewed-on: http://review.coreboot.org/6215 Tested-by: build bot (Jenkins) Reviewed-by: Patrick Georgi <patrick@georgi-clan.de> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Diffstat (limited to 'src/cpu/samsung/exynos5420/clock.c')
-rw-r--r--src/cpu/samsung/exynos5420/clock.c7
1 files changed, 1 insertions, 6 deletions
diff --git a/src/cpu/samsung/exynos5420/clock.c b/src/cpu/samsung/exynos5420/clock.c
index 34d3fb58dc..7ecb717d75 100644
--- a/src/cpu/samsung/exynos5420/clock.c
+++ b/src/cpu/samsung/exynos5420/clock.c
@@ -40,11 +40,6 @@ static struct st_epll_con_val epll_div[] = {
{ 180633600, 0, 45, 3, 1, 10381 }
};
-static inline unsigned long div_round_up(unsigned int n, unsigned int d)
-{
- return (n + d - 1) / d;
-}
-
/* exynos5: return pll clock frequency */
unsigned long get_pll_clk(int pllreg)
{
@@ -346,7 +341,7 @@ int clock_set_dwmci(enum periph_id peripheral)
if (!sclk) {
return -1;
}
- div = div_round_up(sclk, freq);
+ div = CEIL_DIV(sclk, freq);
set_mmc_clk(device_index, div);
return 0;
}