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authorDavid Hendricks <dhendrix@chromium.org>2013-08-08 19:03:03 -0700
committerPatrick Georgi <patrick@georgi-clan.de>2013-12-21 22:46:33 +0100
commitefd4b9e936d11816cec3f4ab1aa3d897c8cfd0e5 (patch)
treeb67d53d2b45e58a44238ef4a637d412ada427587 /src/cpu/samsung/exynos5420/Kconfig
parent5f6ffbab1b67ed34aac4b85ae9e64dbd08e373f2 (diff)
exynos5420: add a peripheral clock select --> PLL decoder
This adds a helper function to translate between peripheral clock select fields in clock source registers and PLLs. Some of this was already done to handle a few special cases, this generalizes the earlier work so that follow-up patches can do further clean-up. Unfortunately, the PLLs represented by clock select fields in various modules are not uniformly ordered. So for now we focus on peripheral clock sources only. Signed-off-by: David Hendricks <dhendrix@chromium.org> Change-Id: Id58a3e488650d09e6a35c22d5394fcbf0ee9ddff Reviewed-on: https://gerrit.chromium.org/gerrit/65283 Commit-Queue: David Hendricks <dhendrix@chromium.org> Tested-by: David Hendricks <dhendrix@chromium.org> Reviewed-by: Gabe Black <gabeblack@chromium.org> Reviewed-on: http://review.coreboot.org/4462 Tested-by: build bot (Jenkins) Reviewed-by: Patrick Georgi <patrick@georgi-clan.de>
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