exynos5: Refactor board-specific parts out of USB PHY code

This patch moves around some of the existing Exynos5 USB 2.0 PHY code
to make it cleaner in preparation of the 3.0 PHYs. It moves the VBUS
GPIOs (which are completely board-specific) into the mainboard code and
makes sure to only initialize PHYs on the boards that actually need
them. It also removes the USB 3.0 PLL hack that was needed on Snow from
the Pit and Kirby boards (which do not have that PLL anymore).

Change-Id: Ia35f47a765acff60481f0907f7448ec4f78e0937
Signed-off-by: Julius Werner <jwerner@chromium.org>
Reviewed-on: https://gerrit.chromium.org/gerrit/66887
Reviewed-by: Stefan Reinauer <reinauer@google.com>
(cherry picked from commit c3b1a8b687b535f4d5ac1b3bd2a4760151698fdb)
Signed-off-by: Isaac Christensen <isaac.christensen@se-eng.com>
Reviewed-on: http://review.coreboot.org/6609
Tested-by: build bot (Jenkins)
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>

6 files changed, 50 insertions, 97 deletions

diff --git a/src/cpu/samsung/exynos5250/cpu.c b/src/cpu/samsung/exynos5250/cpu.c
index 9a44409402..1ad248d0d1 100644
--- a/src/cpu/samsung/exynos5250/cpu.c
+++ b/src/cpu/samsung/exynos5250/cpu.c
@@ -30,7 +30,6 @@
 #include "dp-core.h"
 #include "cpu.h"
 #include "clk.h"
-#include "usb.h"
 #include "chip.h"
 
 static unsigned int cpu_id;
@@ -153,8 +152,6 @@ static void cpu_init(device_t dev)
 {
 	printk(BIOS_INFO, "CPU:   S5P%X @ %ldMHz\n",
 			cpu_id, get_arm_clk() / (1024*1024));
-
-	usb_init(dev);
 }
 
 static void cpu_noop(device_t dev)
diff --git a/src/cpu/samsung/exynos5250/cpu.h b/src/cpu/samsung/exynos5250/cpu.h
index f4ab3edb21..4cc93916f6 100644
--- a/src/cpu/samsung/exynos5250/cpu.h
+++ b/src/cpu/samsung/exynos5250/cpu.h
@@ -44,9 +44,10 @@
 #define EXYNOS5_DMC_CTRL_BASE		0x10DD0000
 #define EXYNOS5_GPIO_PART1_BASE		0x11400000	/* A00..Y67 */
 #define EXYNOS5_GPIO_PART2_BASE		0x11400c00	/* X00..X37 */
+#define EXYNOS5_USB_DRD_XHCI_BASE	0x12000000
+#define EXYNOS5_USB_DRD_PHY_BASE	0x12100000
 #define EXYNOS5_USB_HOST_EHCI_BASE	0x12110000
-#define EXYNOS5_USBPHY_BASE		0x12130000
-#define EXYNOS5_USBOTG_BASE		0x12140000
+#define EXYNOS5_USB_HOST_PHY_BASE	0x12130000
 
 #define EXYNOS5_MMC_BASE		0x12200000
 #define EXYNOS5_MSHC_BASE		0x12240000
@@ -117,8 +118,9 @@
 #define samsung_get_base_swreset() ((struct exynos5_swreset *)EXYNOS5_SWRESET)
 #define samsung_get_base_sysreg() ((struct exynos5_sysreg *)EXYNOS5_SYSREG_BASE)
 #define samsung_get_base_uart() ((struct exynos5_uart *)EXYNOS5_UART_BASE)
-#define samsung_get_base_usb_phy() ((struct exynos5_usb_phy *)EXYNOS5_USBPHY_BASE)
-#define samsung_get_base_usb_otg() ((struct exynos5_usb_otg *)EXYNOS5_USBOTG_BASE)
+#define samsung_get_base_usb_drd_phy() ((struct exynos5_usb_drd_phy *)EXYNOS5_USB_DRD_PHY_BASE)
+#define samsung_get_base_usb_host_phy() ((struct exynos5_usb_host_phy *)EXYNOS5_USB_HOST_PHY_BASE)
+#define samsung_get_base_usb_host_otg() ((struct exynos5_usb_host_otg *)EXYNOS5_USB_HOST_OTG_BASE)
 #define samsung_get_base_watchdog() ((struct exynos5_watchdog *)EXYNOS5_WATCHDOG_BASE)
 #define samsung_get_base_power() ((struct exynos5_power *)EXYNOS5_POWER_BASE)
 #define samsung_get_base_i2s() ((struct exynos5_i2s *)EXYNOS5_I2S_BASE)
diff --git a/src/cpu/samsung/exynos5250/power.c b/src/cpu/samsung/exynos5250/power.c
index 029efc98fb..be055e35dd 100644
--- a/src/cpu/samsung/exynos5250/power.c
+++ b/src/cpu/samsung/exynos5250/power.c
@@ -24,7 +24,6 @@
 #include <arch/hlt.h>
 #include "cpu.h"
 #include "power.h"
-#include "sysreg.h"
 
 static void ps_hold_setup(void)
 {
@@ -65,36 +64,6 @@ void power_enable_dp_phy(void)
 	setbits_le32(&power->dptx_phy_control, DPTX_PHY_ENABLE);
 }
 
-void power_enable_usb_phy(void)
-{
-	struct exynos5_sysreg *sysreg =
-		samsung_get_base_sysreg();
-	struct exynos5_power *power =
-		samsung_get_base_power();
-	unsigned int phy_cfg;
-
-	/* Setting USB20PHY_CONFIG register to USB 2.0 HOST link */
-	phy_cfg = readl(&sysreg->usb20_phy_cfg);
-	if (phy_cfg & USB20_PHY_CFG_EN) {
-		printk(BIOS_DEBUG, "USB 2.0 HOST link already selected\n");
-	} else {
-		phy_cfg |= USB20_PHY_CFG_EN;
-		writel(phy_cfg, &sysreg->usb20_phy_cfg);
-	}
-
-	/* Enabling USBHOST_PHY */
-	setbits_le32(&power->usb_host_phy_ctrl, POWER_USB_HOST_PHY_CTRL_EN);
-}
-
-void power_disable_usb_phy(void)
-{
-	struct exynos5_power *power =
-		samsung_get_base_power();
-
-	/* Disabling USBHost_PHY */
-	clrbits_le32(&power->usb_host_phy_ctrl, POWER_USB_HOST_PHY_CTRL_EN);
-}
-
 void power_enable_hw_thermal_trip(void)
 {
 	struct exynos5_power *power =
diff --git a/src/cpu/samsung/exynos5250/power.h b/src/cpu/samsung/exynos5250/power.h
index 5483d92de4..2b57e18ec4 100644
--- a/src/cpu/samsung/exynos5250/power.h
+++ b/src/cpu/samsung/exynos5250/power.h
@@ -73,9 +73,6 @@ void power_shutdown(void);
 /* Enable DPTX PHY */
 void power_enable_dp_phy(void);
 
-void power_enable_usb_phy(void);
-void power_disable_usb_phy(void);
-
 /* Initialize the pmic voltages to power up the system */
 int power_init(void);
 
diff --git a/src/cpu/samsung/exynos5250/usb.c b/src/cpu/samsung/exynos5250/usb.c
index 5084707e36..9e990a1137 100644
--- a/src/cpu/samsung/exynos5250/usb.c
+++ b/src/cpu/samsung/exynos5250/usb.c
@@ -18,75 +18,72 @@
  * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
  */
 
+#include <delay.h>
+#include <arch/io.h>
 #include <console/console.h>
 #include <device/device.h>
-#include <arch/io.h>
-#include <delay.h>
+#include "cpu.h"
 #include "gpio.h"
 #include "power.h"
-#include "cpu.h"
+#include "sysreg.h"
 #include "usb.h"
-#include "chip.h"
 
-/* Enable VBUS */
-static int usb_vbus_init(int vbus_gpio)
-{
-	/* Enable VBUS power switch */
-	gpio_direction_output(GPIO_X11, 1);
-	/* VBUS turn ON time */
-	mdelay(3);
-
-	return 0;
-}
-
-/* Setup the EHCI host controller. */
-
-static void setup_usb_phy(struct usb_phy *usb, int hsic_gpio)
+void setup_usb_host_phy(int hsic_gpio)
 {
 	unsigned int hostphy_ctrl0;
+	struct exynos5_sysreg *sysreg = samsung_get_base_sysreg();
+	struct exynos5_power *power = samsung_get_base_power();
+	struct exynos5_usb_host_phy *phy = samsung_get_base_usb_host_phy();
 
-	power_enable_usb_phy();
+	setbits_le32(&sysreg->usb20_phy_cfg, USB20_PHY_CFG_EN);
+	setbits_le32(&power->usb_host_phy_ctrl, POWER_USB_HOST_PHY_CTRL_EN);
 
-	/* Setting up host and device simultaneously */
-	hostphy_ctrl0 = readl(&usb->usbphyctrl0);
-	hostphy_ctrl0 &= ~(HOST_CTRL0_FSEL_MASK | HOST_CTRL0_COMMONON_N |
+	printk(BIOS_DEBUG, "Powering up USB HOST PHY (%s HSIC)\n",
+			hsic_gpio ? "with" : "without");
+
+	hostphy_ctrl0 = readl(&phy->usbphyctrl0);
+	hostphy_ctrl0 &= ~(HOST_CTRL0_FSEL_MASK |
+			   HOST_CTRL0_COMMONON_N |
 			   /* HOST Phy setting */
 			   HOST_CTRL0_PHYSWRST |
 			   HOST_CTRL0_PHYSWRSTALL |
 			   HOST_CTRL0_SIDDQ |
 			   HOST_CTRL0_FORCESUSPEND |
 			   HOST_CTRL0_FORCESLEEP);
-	hostphy_ctrl0 |= (	/* Setting up the ref freq */
-				 CLK_24MHZ << 16 |
-				 /* HOST Phy setting */
-				 HOST_CTRL0_LINKSWRST |
-				 HOST_CTRL0_UTMISWRST);
-	writel(hostphy_ctrl0, &usb->usbphyctrl0);
+	hostphy_ctrl0 |= (/* Setting up the ref freq */
+			  CLK_24MHZ << 16 |
+			  /* HOST Phy setting */
+			  HOST_CTRL0_LINKSWRST |
+			  HOST_CTRL0_UTMISWRST);
+	writel(hostphy_ctrl0, &phy->usbphyctrl0);
 	udelay(10);
-	clrbits_le32(&usb->usbphyctrl0,
-		     HOST_CTRL0_LINKSWRST | HOST_CTRL0_UTMISWRST);
+	clrbits_le32(&phy->usbphyctrl0,
+		     HOST_CTRL0_LINKSWRST |
+		     HOST_CTRL0_UTMISWRST);
 	udelay(20);
 
 	/* EHCI Ctrl setting */
-	setbits_le32(&usb->ehcictrl,
+	setbits_le32(&phy->ehcictrl,
 		     EHCICTRL_ENAINCRXALIGN |
 		     EHCICTRL_ENAINCR4 |
-		     EHCICTRL_ENAINCR8 | EHCICTRL_ENAINCR16);
+		     EHCICTRL_ENAINCR8 |
+		     EHCICTRL_ENAINCR16);
 
 	/* HSIC USB Hub initialization. */
-	// FIXME board specific?
-	gpio_direction_output(hsic_gpio, 0);
-	udelay(100);
-	gpio_direction_output(hsic_gpio, 1);
-	udelay(5000);
+	if (hsic_gpio) {
+		gpio_direction_output(hsic_gpio, 0);
+		udelay(100);
+		gpio_direction_output(hsic_gpio, 1);
+		udelay(5000);
 
-	clrbits_le32(&usb->hsicphyctrl1,
-		     HOST_CTRL0_SIDDQ |
-		     HOST_CTRL0_FORCESLEEP |
-		     HOST_CTRL0_FORCESUSPEND);
-	setbits_le32(&usb->hsicphyctrl1, HOST_CTRL0_PHYSWRST);
-	udelay(10);
-	clrbits_le32(&usb->hsicphyctrl1, HOST_CTRL0_PHYSWRST);
+		clrbits_le32(&phy->hsicphyctrl1,
+			     HOST_CTRL0_SIDDQ |
+			     HOST_CTRL0_FORCESLEEP |
+			     HOST_CTRL0_FORCESUSPEND);
+		setbits_le32(&phy->hsicphyctrl1, HOST_CTRL0_PHYSWRST);
+		udelay(10);
+		clrbits_le32(&phy->hsicphyctrl1, HOST_CTRL0_PHYSWRST);
+	}
 
 	/* At this point we need to wait for 50ms before talking to
 	 * the USB controller (PHY clock and power setup time)
@@ -94,13 +91,3 @@ static void setup_usb_phy(struct usb_phy *usb, int hsic_gpio)
 	 * will have passed.
 	 */
 }
-
-void usb_init(device_t dev)
-{
-	struct usb_phy *usb;
-	struct cpu_samsung_exynos5250_config *conf = dev->chip_info;
-
-	usb_vbus_init(conf->usb_vbus_gpio);
-	usb = (struct usb_phy *) samsung_get_base_usb_phy();
-	setup_usb_phy(usb, conf->usb_hsic_gpio);
-}
diff --git a/src/cpu/samsung/exynos5250/usb.h b/src/cpu/samsung/exynos5250/usb.h
index 45a7b53b0a..c963436602 100644
--- a/src/cpu/samsung/exynos5250/usb.h
+++ b/src/cpu/samsung/exynos5250/usb.h
@@ -40,7 +40,7 @@
 #define EHCICTRL_ENAINCR16                      (1 << 26)
 
 /* Register map for PHY control */
-struct usb_phy {
+struct exynos5_usb_host_phy {
         uint32_t usbphyctrl0;
         uint32_t usbphytune0;
         uint32_t reserved1[2];
@@ -57,6 +57,7 @@ struct usb_phy {
         uint32_t usbotgtune;
 };
 
-void usb_init(device_t dev);
+/* Leave hsic_gpio at 0 to not enable HSIC. */
+void setup_usb_host_phy(int hsic_gpio);
 
 #endif