diff options
| author | Julius Werner <jwerner@chromium.org> | 2013-08-15 17:34:45 -0700 |
|---|---|---|
| committer | Isaac Christensen <isaac.christensen@se-eng.com> | 2014-08-12 22:05:17 +0200 |
| commit | 79bff70ac829f45b27650671f9c33028c4b8f6c7 (patch) | |
| tree | 39181ed154fa3f8733b4623b1e210fe3db355f2c /src/cpu/samsung/exynos5250/cpu.h | |
| parent | e9738dbe2bb564f7be7930aa5b01e9ae3c1e2288 (diff) | |
exynos5: Refactor board-specific parts out of USB PHY code
This patch moves around some of the existing Exynos5 USB 2.0 PHY code
to make it cleaner in preparation of the 3.0 PHYs. It moves the VBUS
GPIOs (which are completely board-specific) into the mainboard code and
makes sure to only initialize PHYs on the boards that actually need
them. It also removes the USB 3.0 PLL hack that was needed on Snow from
the Pit and Kirby boards (which do not have that PLL anymore).
Change-Id: Ia35f47a765acff60481f0907f7448ec4f78e0937
Signed-off-by: Julius Werner <jwerner@chromium.org>
Reviewed-on: https://gerrit.chromium.org/gerrit/66887
Reviewed-by: Stefan Reinauer <reinauer@google.com>
(cherry picked from commit c3b1a8b687b535f4d5ac1b3bd2a4760151698fdb)
Signed-off-by: Isaac Christensen <isaac.christensen@se-eng.com>
Reviewed-on: http://review.coreboot.org/6609
Tested-by: build bot (Jenkins)
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
Diffstat (limited to 'src/cpu/samsung/exynos5250/cpu.h')
| -rw-r--r-- | src/cpu/samsung/exynos5250/cpu.h | 10 |
1 files changed, 6 insertions, 4 deletions
diff --git a/src/cpu/samsung/exynos5250/cpu.h b/src/cpu/samsung/exynos5250/cpu.h index f4ab3edb21..4cc93916f6 100644 --- a/src/cpu/samsung/exynos5250/cpu.h +++ b/src/cpu/samsung/exynos5250/cpu.h @@ -44,9 +44,10 @@ #define EXYNOS5_DMC_CTRL_BASE 0x10DD0000 #define EXYNOS5_GPIO_PART1_BASE 0x11400000 /* A00..Y67 */ #define EXYNOS5_GPIO_PART2_BASE 0x11400c00 /* X00..X37 */ +#define EXYNOS5_USB_DRD_XHCI_BASE 0x12000000 +#define EXYNOS5_USB_DRD_PHY_BASE 0x12100000 #define EXYNOS5_USB_HOST_EHCI_BASE 0x12110000 -#define EXYNOS5_USBPHY_BASE 0x12130000 -#define EXYNOS5_USBOTG_BASE 0x12140000 +#define EXYNOS5_USB_HOST_PHY_BASE 0x12130000 #define EXYNOS5_MMC_BASE 0x12200000 #define EXYNOS5_MSHC_BASE 0x12240000 @@ -117,8 +118,9 @@ #define samsung_get_base_swreset() ((struct exynos5_swreset *)EXYNOS5_SWRESET) #define samsung_get_base_sysreg() ((struct exynos5_sysreg *)EXYNOS5_SYSREG_BASE) #define samsung_get_base_uart() ((struct exynos5_uart *)EXYNOS5_UART_BASE) -#define samsung_get_base_usb_phy() ((struct exynos5_usb_phy *)EXYNOS5_USBPHY_BASE) -#define samsung_get_base_usb_otg() ((struct exynos5_usb_otg *)EXYNOS5_USBOTG_BASE) +#define samsung_get_base_usb_drd_phy() ((struct exynos5_usb_drd_phy *)EXYNOS5_USB_DRD_PHY_BASE) +#define samsung_get_base_usb_host_phy() ((struct exynos5_usb_host_phy *)EXYNOS5_USB_HOST_PHY_BASE) +#define samsung_get_base_usb_host_otg() ((struct exynos5_usb_host_otg *)EXYNOS5_USB_HOST_OTG_BASE) #define samsung_get_base_watchdog() ((struct exynos5_watchdog *)EXYNOS5_WATCHDOG_BASE) #define samsung_get_base_power() ((struct exynos5_power *)EXYNOS5_POWER_BASE) #define samsung_get_base_i2s() ((struct exynos5_i2s *)EXYNOS5_I2S_BASE) |