diff options
author | Stefan Reinauer <reinauer@chromium.org> | 2013-05-14 13:32:33 -0700 |
---|---|---|
committer | Stefan Reinauer <stefan.reinauer@coreboot.org> | 2013-07-10 02:41:23 +0200 |
commit | b98dec032f0d8ee158e606bceef9766a905ad503 (patch) | |
tree | fce643a46c82ab71e3778a9c798fb4fac7702371 /src/cpu/samsung/exynos5250/Makefile.inc | |
parent | 043eb0e35f93b41348eb69061a6aa0355ef544bc (diff) |
samsung/exynos5250: unify code
It turns out that the exynos5-common code previously imported from
u-boot is not common code at all but very specific to the 5250 and
not compatible with the 5450. Hence, unify the directories exynos5250
and exynos5-common. We will try to factor out common code while
progressing with the 5450 port.
Change-Id: Iab595e66fcd01eda8365c96fb8bef896f7602f03
Signed-off-by: Stefan Reinauer <reinauer@google.com>
Signed-off-by: Gabe Black <gabeblack@chromium.org>
Reviewed-on: http://review.coreboot.org/3641
Tested-by: build bot (Jenkins)
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
Diffstat (limited to 'src/cpu/samsung/exynos5250/Makefile.inc')
-rw-r--r-- | src/cpu/samsung/exynos5250/Makefile.inc | 21 |
1 files changed, 20 insertions, 1 deletions
diff --git a/src/cpu/samsung/exynos5250/Makefile.inc b/src/cpu/samsung/exynos5250/Makefile.inc index 6449714a51..d89bc95ce2 100644 --- a/src/cpu/samsung/exynos5250/Makefile.inc +++ b/src/cpu/samsung/exynos5250/Makefile.inc @@ -3,6 +3,7 @@ # image outside of CBFS INTERMEDIATE += exynos5250_add_bl1 +bootblock-y += spi.c bootblock-y += pinmux.c mct.c power.c # Clock is required for UART bootblock-$(CONFIG_EARLY_CONSOLE) += clock_init.c @@ -11,7 +12,11 @@ bootblock-$(CONFIG_EARLY_CONSOLE) += monotonic_timer.c bootblock-$(CONFIG_EARLY_CONSOLE) += soc.c bootblock-$(CONFIG_EARLY_CONSOLE) += uart.c bootblock-y += wakeup.c +bootblock-y += gpio.c +bootblock-$(CONFIG_EARLY_CONSOLE) += pwm.c +bootblock-$(CONFIG_EARLY_CONSOLE) += timer.c +romstage-y += spi.c romstage-y += clock.c romstage-y += clock_init.c romstage-y += pinmux.c # required by s3c24x0_i2c (exynos5-common) and uart. @@ -23,7 +28,14 @@ romstage-y += monotonic_timer.c romstage-$(CONFIG_EARLY_CONSOLE) += soc.c romstage-$(CONFIG_EARLY_CONSOLE) += uart.c romstage-y += wakeup.c +romstage-y += pwm.c # needed by timer.c +romstage-y += gpio.c +romstage-y += timer.c +romstage-y += i2c.c +#romstage-y += wdt.c +#romstage-y += sromc.c +ramstage-y += spi.c #ramstage-y += tzpc_init.c ramstage-y += clock.c ramstage-y += clock_init.c @@ -35,8 +47,15 @@ ramstage-y += cpu.c ramstage-y += exynos5250-tmu.c ramstage-y += mct.c ramstage-y += monotonic_timer.c - #ramstage-$(CONFIG_SATA_AHCI) += sata.c +ramstage-y += cpu_info.c +ramstage-y += pwm.c # needed by timer.c +ramstage-y += timer.c +ramstage-y += gpio.c +ramstage-y += i2c.c +ramstage-y += s5p-dp-reg.c +ramstage-y += exynos-fb.c +ramstage-y += exynos-tmu.c exynos5250_add_bl1: $(obj)/coreboot.pre printf " DD Adding Samsung Exynos5250 BL1\n" |