armv7/snow: get to romstage

This patch does a few things to get us into romstage:
- Add romstage as a stage (a later patch adds it as a binary, which
  is probably wrong). The Makefile magic is complex enough that we
  let it build the XIP file for now, but we no longer use it.

- Replace findstage with loadstage. Loadstage will find a stage,
  load the code to memory, and zero the remaining part of memory.
  Now we can link the romstage to go anywhere!

- Eliminate magic offsets from code/ldscripts and centralize Kconfig
  variables in src/cpu/samsung/exynos5250/Kconfig.

- Tidy up code and serial output

Change-Id: Iae4d2f9e7f429cb1df15d49daf9a08b88d75d79d
Signed-off-by: David Hendricks <dhendrix@chromium.org>
Signed-off-by: Ronald G. Minnich <rminnich@gmail.com>
Reviewed-on: http://review.coreboot.org/2174
Tested-by: build bot (Jenkins)

1 files changed, 53 insertions, 24 deletions

diff --git a/src/cpu/samsung/exynos5250/Kconfig b/src/cpu/samsung/exynos5250/Kconfig
index 206df9260b..f5beddcdb4 100644
--- a/src/cpu/samsung/exynos5250/Kconfig
+++ b/src/cpu/samsung/exynos5250/Kconfig
@@ -14,43 +14,72 @@ config SATA_AHCI
 	bool
 	default n
 
-config SPL_BUILD
-	bool
-	default n
+# Example SRAM/iRAM map for Exynos5250 platform:
+#
+# 0x0202_0000: vendor-provided BL1
+# 0x0202_3400: bootblock, assume up to 32KB in size
+# 0x0202_2600: ID section, assume 2KB in size. This will be
+#              within the bootblock section.
+# 0x0203_0000: romstage, assume up to 128KB in size.
+# 0x0207_7f00: stack pointer
 
-config SYS_TEXT_BASE
-	hex "Executable code section"
-	default 0x43e00000
+# this may be used to calculate offsets
+config IRAM_BOTTOM
+	hex
+	default 0x02020000
 
-config SYS_SDRAM_BASE
-	hex "SDRAM base address"
-	default 0x40000000
+config IRAM_TOP
+	hex
+	default 0x02077fff
 
-#FIXME(dhendrix, reinauer): re-visit this RAMBASE/RAMTOP stuff...
-config RAMBASE
+config BOOTBLOCK_BASE
 	hex
-	default SYS_SDRAM_BASE
-# according to stefan, this is RAMBASE + 1M.
-config RAMTOP
+	default 0x02023400
+
+config ID_SECTION_BASE
 	hex
-	default 0x40100000
+	default 0x02026000
 
-config IRAM_BOTTOM
+config ROMSTAGE_BASE
 	hex
-	default 0x02020000
+	default 0x02030000
 
-config IRAM_TOP
+config ROMSTAGE_SIZE
 	hex
-	default 0x02077fff
+	default 0x10000
 
-config SYS_INIT_SP_ADDR
+# FIXME: This is for copying SPI content into SRAM temporarily and
+# will be removed when we have the SPI streaming driver implemented.
+config SPI_IMAGE_HACK
 	hex
-	default 0x02058000
+	default 0x02060000
 
 config IRAM_STACK
 	hex
-	default SYS_INIT_SP_ADDR
+	default 0x02077f00
 
+# FIXME: other magic numbers that should probably go away
 config XIP_ROM_SIZE
-	hex "ROM stage (BL2) size"
-	default 0x20000
+	hex
+	default ROMSTAGE_SIZE
+
+config SYS_SDRAM_BASE
+	hex "SDRAM base address"
+	default 0x40000000
+
+config SPL_BUILD
+	bool
+	default n
+
+config SYS_TEXT_BASE
+	hex "Executable code section"
+	default 0x43e00000
+
+config RAMBASE
+	hex
+	default SYS_SDRAM_BASE
+# according to stefan, this is RAMBASE + 1M.
+config RAMTOP
+	hex
+	default 0x40100000
+