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author | Felix Held <felix-coreboot@felixheld.de> | 2022-08-17 21:38:07 +0200 |
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committer | Felix Held <felix-coreboot@felixheld.de> | 2022-08-20 20:43:17 +0000 |
commit | f7d86f21e12aa3a368aa87aa4a1406e7c38e07b0 (patch) | |
tree | dca5058f114765b2fe2bf97767a1394a720c79c4 /src/cpu/qemu-x86 | |
parent | e943e9fc241a50494ff846dce01da33468fe989b (diff) |
soc/amd/stoneyridge/early_fch: use common lpc_early_init function
The functionality of sb_enable_lpc is implemented in the common LPC
support code as lpc_enable_controller. This gets called by the common
lpc_early_init which also calls lpc_disable_decodes and lpc_set_spibase.
The lpc_set_spibase call was already done in bootblock_fch_early_init,
so the main change in code behavior is that now lpc_disable_decodes gets
called during early FCH initialization. The lpc_enable_port80 and
sb_lpc_decode calls after the lpc_early_init code will reenable some of
the decodes.
TEST=Successfully boots on google/liara, cbmem and dmesg logs look clean
Signed-off-by: Felix Held <felix-coreboot@felixheld.de>
Change-Id: Ia58a6f609fa149a6c09ed99f08bdc4f05eb56f96
Reviewed-on: https://review.coreboot.org/c/coreboot/+/66841
Reviewed-by: Matt DeVillier <matt.devillier@amd.corp-partner.google.com>
Reviewed-by: Raul Rangel <rrangel@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Diffstat (limited to 'src/cpu/qemu-x86')
0 files changed, 0 insertions, 0 deletions