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authorStefan Reinauer <stepan@coresystems.de>2008-01-18 15:08:58 +0000
committerStefan Reinauer <stepan@openbios.org>2008-01-18 15:08:58 +0000
commitf8ee1806ac524bc782c93eccc59ee3c929abddb9 (patch)
tree7daab6b3aa82476a10d38fbf68068f4a409d2ce9 /src/cpu/ppc/ppc7xx
parent7e61e45402aba2b90997f4f02ca8266cf65a229a (diff)
Rename almost all occurences of LinuxBIOS to coreboot.
Due to the automatic nature of this update, I am self-acking. It worked in abuild. Signed-off-by: Stefan Reinauer <stepan@coresystems.de> Acked-by: Stefan Reinauer <stepan@coresystems.de> git-svn-id: svn://svn.coreboot.org/coreboot/trunk@3053 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
Diffstat (limited to 'src/cpu/ppc/ppc7xx')
-rw-r--r--src/cpu/ppc/ppc7xx/Config.lb2
-rw-r--r--src/cpu/ppc/ppc7xx/ppc7xx.inc4
2 files changed, 3 insertions, 3 deletions
diff --git a/src/cpu/ppc/ppc7xx/Config.lb b/src/cpu/ppc/ppc7xx/Config.lb
index dc2c025511..d6e64b379b 100644
--- a/src/cpu/ppc/ppc7xx/Config.lb
+++ b/src/cpu/ppc/ppc7xx/Config.lb
@@ -10,7 +10,7 @@ uses DCACHE_RAM_SIZE
## PPC7XX always uses cache ram for initial setup
##
default USE_DCACHE_RAM=1
-## Set dcache ram above linuxbios image
+## Set dcache ram above coreboot image
default DCACHE_RAM_BASE=_RAMBASE+0x100000
## Dcache size is 16Kb
default DCACHE_RAM_SIZE=16384
diff --git a/src/cpu/ppc/ppc7xx/ppc7xx.inc b/src/cpu/ppc/ppc7xx/ppc7xx.inc
index 11b54c4207..bd599f324e 100644
--- a/src/cpu/ppc/ppc7xx/ppc7xx.inc
+++ b/src/cpu/ppc/ppc7xx/ppc7xx.inc
@@ -19,7 +19,7 @@
/*
* The aim of this code is to bring the machine from power-on to the point
- * where we can jump to the the main LinuxBIOS entry point hardwaremain()
+ * where we can jump to the the main coreboot entry point hardwaremain()
* which is written in C.
*
* At power-on, we have no RAM, a memory-mapped I/O space, and we are executing
@@ -72,7 +72,7 @@
isync
/*
- * Clear segment registers (LinuxBIOS doesn't use these)
+ * Clear segment registers (coreboot doesn't use these)
*/
li r3, 15
1: mtsrin r3, r0