diff options
| author | Stefan Reinauer <stepan@coresystems.de> | 2009-06-30 15:17:49 +0000 |
|---|---|---|
| committer | Stefan Reinauer <stepan@openbios.org> | 2009-06-30 15:17:49 +0000 |
| commit | 0867062412dd4bfe5a556e5f3fd85ba5b682d79b (patch) | |
| tree | 81ca5db12b8567b48daaa23a541bfb8a5dc011f8 /src/cpu/ppc/ppc7xx | |
| parent | 9702b6bf7ec5a4fb16934f1cf2724480e2460c89 (diff) | |
This patch unifies the use of config options in v2 to all start with CONFIG_
It's basically done with the following script and some manual fixup:
VARS=`grep ^define src/config/Options.lb | cut -f2 -d\ | grep -v ^CONFIG | grep -v ^COREBOOT |grep -v ^CC`
for VAR in $VARS; do
find . -name .svn -prune -o -type f -exec perl -pi -e "s/(^|[^0-9a-zA-Z_]+)$VAR($|[^0-9a-zA-Z_]+)/\1CONFIG_$VAR\2/g" {} \;
done
Signed-off-by: Stefan Reinauer <stepan@coresystems.de>
Acked-by: Ronald G. Minnich <rminnich@gmail.com>
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@4381 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
Diffstat (limited to 'src/cpu/ppc/ppc7xx')
| -rw-r--r-- | src/cpu/ppc/ppc7xx/Config.lb | 14 | ||||
| -rw-r--r-- | src/cpu/ppc/ppc7xx/ppc7xx.inc | 14 |
2 files changed, 14 insertions, 14 deletions
diff --git a/src/cpu/ppc/ppc7xx/Config.lb b/src/cpu/ppc/ppc7xx/Config.lb index 521045b1bc..a04a777a06 100644 --- a/src/cpu/ppc/ppc7xx/Config.lb +++ b/src/cpu/ppc/ppc7xx/Config.lb @@ -1,19 +1,19 @@ ## ## CPU initialization ## -uses _RAMBASE -uses USE_DCACHE_RAM -uses DCACHE_RAM_BASE -uses DCACHE_RAM_SIZE +uses CONFIG_RAMBASE +uses CONFIG_USE_DCACHE_RAM +uses CONFIG_DCACHE_RAM_BASE +uses CONFIG_DCACHE_RAM_SIZE ## ## PPC7XX always uses cache ram for initial setup ## -default USE_DCACHE_RAM=1 +default CONFIG_USE_DCACHE_RAM=1 ## Set dcache ram above coreboot image -default DCACHE_RAM_BASE=_RAMBASE+0x100000 +default CONFIG_DCACHE_RAM_BASE=CONFIG_RAMBASE+0x100000 ## Dcache size is 16Kb -default DCACHE_RAM_SIZE=16384 +default CONFIG_DCACHE_RAM_SIZE=16384 initinclude "FAMILY_INIT" cpu/ppc/ppc7xx/ppc7xx.inc diff --git a/src/cpu/ppc/ppc7xx/ppc7xx.inc b/src/cpu/ppc/ppc7xx/ppc7xx.inc index bd599f324e..4f8ab86da3 100644 --- a/src/cpu/ppc/ppc7xx/ppc7xx.inc +++ b/src/cpu/ppc/ppc7xx/ppc7xx.inc @@ -30,7 +30,7 @@ * - enable L1 I/D caches, otherwise performance will be slow * - set up DBATs for the following regions: * - RAM (generally 0x00000000 -> 0x7fffffff) - * - ROM (_ROMBASE -> _ROMBASE + ROM_SIZE) + * - ROM (CONFIG_ROMBASE -> CONFIG_ROMBASE + CONFIG_ROM_SIZE) * - I/O (generally 0xfc000000 -> 0xfdffffff) * - the main purpose for setting up the DBATs is so the I/O region * can be marked cache inhibited/write through @@ -113,7 +113,7 @@ * IBATS * * IBAT0 covers RAM (0 -> 256Mb) - * IBAT1 covers ROM (_ROMBASE -> _ROMBASE+ROM_SIZE) + * IBAT1 covers ROM (CONFIG_ROMBASE -> CONFIG_ROMBASE+CONFIG_ROM_SIZE) */ lis r2, 0@h ori r3, r2, BAT_BL_256M | BAT_VALID_SUPERVISOR | BAT_VALID_USER @@ -122,8 +122,8 @@ mtibatl 0, r2 isync - lis r2, _ROMBASE@h -#if ROM_SIZE > 1048576 + lis r2, CONFIG_ROMBASE@h +#if CONFIG_ROM_SIZE > 1048576 ori r3, r2, BAT_BL_16M | BAT_VALID_SUPERVISOR | BAT_VALID_USER #else ori r3, r2, BAT_BL_1M | BAT_VALID_SUPERVISOR | BAT_VALID_USER @@ -161,9 +161,9 @@ * Initialize data cache blocks * (assumes cache block size of 32 bytes) */ - lis r1, DCACHE_RAM_BASE@h - ori r1, r1, DCACHE_RAM_BASE@l - li r3, (DCACHE_RAM_SIZE / 32) + lis r1, CONFIG_DCACHE_RAM_BASE@h + ori r1, r1, CONFIG_DCACHE_RAM_BASE@l + li r3, (CONFIG_DCACHE_RAM_SIZE / 32) mtctr r3 0: dcbz r0, r1 addi r1, r1, 32 |