diff options
| author | Stefan Reinauer <stepan@coresystems.de> | 2008-01-18 15:08:58 +0000 |
|---|---|---|
| committer | Stefan Reinauer <stepan@openbios.org> | 2008-01-18 15:08:58 +0000 |
| commit | f8ee1806ac524bc782c93eccc59ee3c929abddb9 (patch) | |
| tree | 7daab6b3aa82476a10d38fbf68068f4a409d2ce9 /src/cpu/ppc/ppc4xx | |
| parent | 7e61e45402aba2b90997f4f02ca8266cf65a229a (diff) | |
Rename almost all occurences of LinuxBIOS to coreboot.
Due to the automatic nature of this update, I am self-acking. It worked in
abuild.
Signed-off-by: Stefan Reinauer <stepan@coresystems.de>
Acked-by: Stefan Reinauer <stepan@coresystems.de>
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@3053 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
Diffstat (limited to 'src/cpu/ppc/ppc4xx')
| -rw-r--r-- | src/cpu/ppc/ppc4xx/Config.lb | 2 |
1 files changed, 1 insertions, 1 deletions
diff --git a/src/cpu/ppc/ppc4xx/Config.lb b/src/cpu/ppc/ppc4xx/Config.lb index 4bf4638762..f739495325 100644 --- a/src/cpu/ppc/ppc4xx/Config.lb +++ b/src/cpu/ppc/ppc4xx/Config.lb @@ -10,7 +10,7 @@ uses DCACHE_RAM_SIZE ## PPC4XX always uses cache ram for initial setup ## default USE_DCACHE_RAM=1 -## Set dcache ram above linuxbios image +## Set dcache ram above coreboot image default DCACHE_RAM_BASE=_RAMBASE+0x100000 ## Dcache size is 16Kb default DCACHE_RAM_SIZE=16384 |