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| author | Greg Watson <jarrah@users.sourceforge.net> | 2004-01-14 17:21:22 +0000 |
|---|---|---|
| committer | Greg Watson <jarrah@users.sourceforge.net> | 2004-01-14 17:21:22 +0000 |
| commit | b020d53352c1bbe1084c9c499b45cfb345fc8677 (patch) | |
| tree | 1938b5ec4d8a2e388a19b0a9b38e7497da16b9b4 /src/cpu/ppc/ppc4xx/ppc4xx.inc | |
| parent | bf5b58480129dcd6a770f3f2b237511fb295918e (diff) | |
*** empty log message ***
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@1335 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
Diffstat (limited to 'src/cpu/ppc/ppc4xx/ppc4xx.inc')
| -rw-r--r-- | src/cpu/ppc/ppc4xx/ppc4xx.inc | 10 |
1 files changed, 3 insertions, 7 deletions
diff --git a/src/cpu/ppc/ppc4xx/ppc4xx.inc b/src/cpu/ppc/ppc4xx/ppc4xx.inc index bbd8949a62..eea497734e 100644 --- a/src/cpu/ppc/ppc4xx/ppc4xx.inc +++ b/src/cpu/ppc/ppc4xx/ppc4xx.inc @@ -66,7 +66,7 @@ mtevpr r4 /* clear Exception Vector Prefix Reg */ li r4,0x1000 /* set ME bit (Machine Exceptions) */ oris r4,r4,0x0002 /* set CE bit (Critical Exceptions) */ -// mtmsr r4 /* change MSR */ + mtmsr r4 /* change MSR */ li r4,(0xFFFF-0x10000) /* set r4 to 0xFFFFFFFF (status in */ /* the dbsr is cleared by setting */ /* bits to 1) */ @@ -97,6 +97,8 @@ * Enable dcache region containing DCACHE_RAM_BASE * On reset all regions are set to write-back, so we * just leave them alone. + * + * dccr = (1 << (0x1F - (DCACHE_RAM_BASE >> 27)) */ lis r4, DCACHE_RAM_BASE@ha @@ -107,9 +109,3 @@ slw r4, r0, r4 mtdccr r4 /* data cache enable */ sync - - /* DMA Status, clear to come up clean */ - - addis r3,r0, 0xFFFF /* Clear all existing DMA status */ - ori r3,r3, 0xFFFF - mtdcr dmasr, r3 |