diff options
| author | Kyösti Mälkki <kyosti.malkki@gmail.com> | 2019-09-23 22:58:46 +0300 |
|---|---|---|
| committer | Kyösti Mälkki <kyosti.malkki@gmail.com> | 2019-09-24 19:03:10 +0000 |
| commit | fe26be1181510a0532df632506410d9cab57a20d (patch) | |
| tree | 19f18981ed34ec229f68b3508e2239a15e85787e /src/cpu/intel | |
| parent | be756f18df6ff2fb14cb05e2dab248dd46f4a53e (diff) | |
cpu/intel/common: Fix invalid MSR access
Fix regression from commit ecea916
cpu/intel/common: Extend FSB detection to cover TSC
MSR_EBC_FREQUENCY_ID (0x2c) was not defined for affected
CPU models and rdmsr() caused reset loops. Implementations
deviate from public documentation.
Change to IA32_PERF_STATUS (0x198) already used in i945/udelay.c
to detect FSB to TSC multiplier.
Change-Id: I7a91da221920a7e7bfccb98d76115b5c89e3b52e
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/35548
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
Reviewed-by: HAOUAS Elyes <ehaouas@noos.fr>
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
Diffstat (limited to 'src/cpu/intel')
| -rw-r--r-- | src/cpu/intel/common/fsb.c | 4 |
1 files changed, 2 insertions, 2 deletions
diff --git a/src/cpu/intel/common/fsb.c b/src/cpu/intel/common/fsb.c index 5ad98d4c8f..c32bc235c2 100644 --- a/src/cpu/intel/common/fsb.c +++ b/src/cpu/intel/common/fsb.c @@ -42,12 +42,12 @@ static int get_fsb_tsc(int *fsb, int *ratio) case 0xe: /* Core Solo/Duo */ case 0x1c: /* Atom */ *fsb = core_fsb[rdmsr(MSR_FSB_FREQ).lo & 7]; - *ratio = rdmsr(MSR_EBC_FREQUENCY_ID).lo >> 24; + *ratio = (rdmsr(IA32_PERF_STATUS).hi >> 8) & 0x1f; break; case 0xf: /* Core 2 or Xeon */ case 0x17: /* Enhanced Core */ *fsb = core2_fsb[rdmsr(MSR_FSB_FREQ).lo & 7]; - *ratio = rdmsr(MSR_EBC_FREQUENCY_ID).lo >> 24; + *ratio = (rdmsr(IA32_PERF_STATUS).hi >> 8) & 0x1f; break; case 0x25: /* Nehalem BCLK fixed at 133MHz */ *fsb = 133; |